myhdl-list — Mailing list for discussions on MyHDL

Re: [myhdl-list] combining values in signals

[Edward V. <dev...@sb...>]

Josy r is not a Signal it is a sub band of an image it started out as list. See github develone/jpeg-2000-test/jpeg2k/parellel_jpeg/test_bench_array_jpeg.py typing on cell might ha
have error. Regards thanks


------------------------------
On Tue, Mar 3, 2015 12:34 PM CST Josy Boelen wrote:

>I didn't do it exactly right:
>it should be like this:
>lft_s_i = ConcatSignal( *reversed( [ r[row - 1][col], r[row + 3 + i * 2]
>[col] for i in range(15)] ))
>
>You can, of course, also spell out the list in the call:
>lft_s_i = ConcatSignal( r[row + 31][col], r[row + 29][col], ... , r[row + 
>3][col], r[row - 1][col] ) 
>
>Regards,
>
>Josy
>
>
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Re: [myhdl-list] combining values in signals

[Josy B. <jos...@gm...>]

I didn't do it exactly right:
it should be like this:
lft_s_i = ConcatSignal( *reversed( [ r[row - 1][col], r[row + 3 + i * 2]
[col] for i in range(15)] ))

You can, of course, also spell out the list in the call:
lft_s_i = ConcatSignal( r[row + 31][col], r[row + 29][col], ... , r[row + 
3][col], r[row - 1][col] ) 

Regards,

Josy

Re: [myhdl-list] combining values in signals

[Josy B. <jos...@gm...>]

Edward Vidal <develone <at> sbcglobal.net> writes:

> 
> 
> Hello All,I am creating a 160 bit signals which works okay when the 
values are positive.
> 2130 36 0 0x390e5390e2388e238ce2388e4390df37cdf38ce2L 
0x390e538ce5388e238ce0388e4390e3380e1390e2L 
0x38ce4394e4388e2388e3388e2390e437cdf37ce2L
> W0 is set to 10 each value should take 10 bits. 
lft_s_i.next = (r[row+31][col] << W0*15) + (r[row+29][col] << W0*14) + 
(r[row+27][col] << W0*13) +(r[row+25][col] << W0*12) + (r[row+23][col] 
<< W0*11) + (r[row+21][col] << W0*10) + (r[row+19][col] << W0*9) + 
(r[row+17][col] << W0*8) + (r[row+15][col] << W0*7) + (r[row+13][col] << 
W0*6) + (r[row+11][col] << W0*5) + (r[row+9][col] << W0*4) + (r[row+7]
[col] << W0*3) + (r[row+5][col] << W0*2) + (r[row+3][col] << W0*1) + 
(r[row-1][col] )
<snip>

ConcatSignal( *args ) should do the work. Make a list with all the 
required signals in it and hand that over. Make sure that the most left 
element is first in the list, else reverse the list. Note that the 
result of ConcatSignal() is a Signal in itself. So you don't do this 
inside an always_comb (or similar).
I think you can do it like this:
lft_s_i = ConcatSignal( *reversed( [ r[row - 1 + i * 2][col] for i in 
range(16)] ))
I assume that r is defined as [[Signal(intbv(0)[10:] for _ in 
range(ncol)] for __ in range[nrow)]

Regards,

Josy

[myhdl-list] combining values in signals

[Edward V. <dev...@sb...>]

Hello All,
I am creating a 160 bit signals which works okay when the values are positive.
2130 36 0 0x390e5390e2388e238ce2388e4390df37cdf38ce2L 0x390e538ce5388e238ce0388e4390e3380e1390e2L 0x38ce4394e4388e2388e3388e2390e437cdf37ce2L


W0 is set to 10 each value should take 10 bits. 
lft_s_i.next = (r[row+31][col] << W0*15) + (r[row+29][col] << W0*14) + (r[row+27][col] << W0*13) +(r[row+25][col] << W0*12) + (r[row+23][col] << W0*11) + (r[row+21][col] << W0*10) + (r[row+19][col] << W0*9) + (r[row+17][col] << W0*8) + (r[row+15][col] << W0*7) + (r[row+13][col] << W0*6) + (r[row+11][col] << W0*5) + (r[row+9][col] << W0*4) + (r[row+7][col] << W0*3) + (r[row+5][col] << W0*2) + (r[row+3][col] << W0*1) + (r[row-1][col] )
sa_s_i.next = (r[row+32][col] << W0*15) + (r[row+30][col] << W0*14) + (r[row+28][col] << W0*13) +(r[row+26][col] << W0*12) + (r[row+24][col] << W0*11) + (r[row+22][col] << W0*10) + (r[row+20][col] << W0*9) + (r[row+18][col] << W0*8) + (r[row+16][col] << W0*7) + (r[row+14][col] << W0*6) + (r[row+12][col] << W0*5) + (r[row+10][col] << W0*4) + (r[row+8][col] << W0*3) + (r[row+6][col] << W0*2) + (r[row+4][col] << W0*1) + (r[row][col] )
rht_s_i.next = (r[row+33][col] << W0*15) + (r[row+31][col] << W0*14) + (r[row+29][col] << W0*13) +(r[row+27][col] << W0*12) + (r[row+25][col] << W0*11) + (r[row+23][col] << W0*10) + (r[row+21][col] << W0*9) + (r[row+19][col] << W0*8) + (r[row+17][col] << W0*7) + (r[row+15][col] << W0*6) + (r[row+13][col] << W0*5) + (r[row+11][col] << W0*4) + (r[row+9][col] << W0*3) + (r[row+7][col] << W0*2) + (r[row+5][col] << W0*1) + (r[row+1][col] )

When the values are negative 
now() r[row+31][col]
14592190 -2
now() (r[row+31][col] << W0*15)
14592190 -2854495385411919762116571938898990272765493248
ValueError: intbv value -2857285703481726135295571520461941387401627422 < minimum 0

I tried changing the + to & with the results 0x0L
lft_s_i.next = (r[row+31][col] << W0*15) & (r[row+29][col] << W0*14) & (r[row+27][col] << W0*13) & (r[row+25][col] << W0*12) & (r[row+23][col] << W0*11) & (r[row+21][col] << W0*10) & (r[row+19][col] << W0*9) & (r[row+17][col] << W0*8) & (r[row+15][col] << W0*7) & (r[row+13][col] << W0*6) & (r[row+11][col] << W0*5) & (r[row+9][col] << W0*4) & (r[row+7][col] << W0*3) & (r[row+5][col] << W0*2) & (r[row+3][col] << W0*1) & (r[row-1][col] )
sa_s_i.next = (r[row+32][col] << W0*15) & (r[row+30][col] << W0*14) & (r[row+28][col] << W0*13) & (r[row+26][col] << W0*12) & (r[row+24][col] << W0*11) & (r[row+22][col] << W0*10) & (r[row+20][col] << W0*9) & (r[row+18][col] << W0*8) & (r[row+16][col] << W0*7) & (r[row+14][col] << W0*6) & (r[row+12][col] << W0*5) & (r[row+10][col] << W0*4) & (r[row+8][col] << W0*3) & (r[row+6][col] << W0*2) & (r[row+4][col] << W0*1) & (r[row][col] )
rht_s_i.next = (r[row+33][col] << W0*15) & (r[row+31][col] << W0*14) & (r[row+29][col] << W0*13) & (r[row+27][col] << W0*12) & (r[row+25][col] << W0*11) & (r[row+23][col] << W0*10) & (r[row+21][col] << W0*9) & (r[row+19][col] << W0*8) & (r[row+17][col] << W0*7) & (r[row+15][col] << W0*6) & (r[row+13][col] << W0*5) & (r[row+11][col] << W0*4) & (r[row+9][col] << W0*3) & (r[row+7][col] << W0*2) & (r[row+5][col] << W0*1) & (r[row+1][col] )
Now when the values are positive I get 0x0L
What is the procedure to combine signals.  This is in a test bench right now.
Thanks



 
Edward Vidal Jr.
e-mail dev...@sb...
915-595-1613

Re: [myhdl-list] Prerequisites to run the MyHDL regression test

[Christopher F. <chr...@gm...>]

On 3/1/15 7:50 AM, Josy Boelen wrote:
>
>> You should be fine with the Altera Modelsim then,
>> you can run the `make vcom`.  Are you able to run
>> `make vcom` with git-bash (you might have to add
>> the Altera path) in conversion/general?
>>
>> Regards,
>> Chris
>>
> Chris,
>
> The `make vcom` doesn't work as git-bash expects the .exe extension to
> find `py.test` .

Hmm, that is odd.  On the Windows system I am using
it works - but I don't recall if I did something
custom during setup ...

On the Windows system I am using the Enthought dist
(a Canopy version).  I am fairly sure pytest is
installed with the distro, if it wasn't I probably
installed via `pip`.

> If I give the command `py.test.exe vcom.py test_*.py >utest.log' it seems
> to run, be it with a lot of failures.

Ok, this seems to be an issue because I see the
same thing but I have no idea why (right now).
A quick look it seems the VHDL myhdl pck is
empty, it might be an issue with the latest directory
selection addition.

> But I have `myhdl-0-9-dev` sitting alongside my local `myhdl' and of
> course the test is using this `myhdl`-tree, and I have a few experimental
> changes:

I see all the errors, on Windows only, with no mods.

> like instead of `if bool( sig ) then` I made toVHDL() output`if (sig =
> '1') then`. And the first test fails on that as it has this in the
> converted putput: ` a <= (not (a = '1'))(0);` where the unmodified myhdl
> would have produced ` a <= (not bool(a))(0);`, which I don't quite
> understand either.
>
> The main observation is that I'll have to set up that virtual Linux
> machine anyway.

Possibly but in general I think we want to make
sure things work on most major systems Python
support?  It is odd, from my background most
(not all) FPGA developers work on Windows and most
ASIC devs work on Linux.

Regards,
Chris

Re: [myhdl-list] register-file with variable register size

[Christopher F. <chr...@gm...>]

On 2/13/15 9:09 AM, SHEN Chen wrote:
> Hi Chris,
>
> In fact, I've read some of minnesota's source code yesterday, and find
> it very inspiring.
>
> What I was trying to do is somewhat similar, but if I understand the
> code correctly, you can not write to the read-only register as a whole.

No, you should be able to write the read-only register
as a whole or via the "named-bits".  But the register
can only be one or the other, either it is written by
the "named-bits" or the whole register - not both.

>
> For example, in test_regfile.py we defined "status" as an 'ro' register,
> and declared a few named bits. We can write to the individual bits, but
> not the "status" register as a whole.

Correct, this is because there would be two processes
accessing the register.  It would require some kind of
arbitrator to determine how the register is being
modified.  There might be an elegant solution - but I
have not thought of one?

In your case this register-file builder wouldn't be
useful, sounds like you might need custom logic for
each register definition.

>
> In particular, we can not write the "status" register through its
> address either, which I need in my application.

Correct, in this abstraction only two types of registers
can exist, from the bus masters point of view there are
'rw' registers and 'ro' registers.  The peripheral can
only set the 'ro' registers and the peripheral can only
read the 'rw' registers..  You can't really mix control
and status in the same registers (in this builder).

In general you can mix them but this requires custom logic
per register.  The `RegisterFile` attempts to provide a
register file builder from a simple definition that is
bus agnostic.  Each peripheral (core) can be passed a
different bus type (Wishbone, Avalon, AMBA, etc.) and it
"just works" (well, we will see yet to be proven :)

I had some outstanding issue with the `RegisterFile` that
I have fixed and I will probably be changing and updating
some of the functionality.

I understand the `mn.system.RegsiterFile` doesn't meet
the requirements you currently have but wanted to follow-up
to the previous comments.

Regards,
Chris

Re: [myhdl-list] Prerequisites to run the MyHDL regression test

[Josy B. <jos...@gm...>]

> You should be fine with the Altera Modelsim then,
> you can run the `make vcom`.  Are you able to run
> `make vcom` with git-bash (you might have to add
> the Altera path) in conversion/general?
> 
> Regards,
> Chris
> 
Chris,

The `make vcom` doesn't work as git-bash expects the .exe extension to 
find `py.test` . 
If I give the command `py.test.exe vcom.py test_*.py >utest.log' it seems 
to run, be it with a lot of failures. 
But I have `myhdl-0-9-dev` sitting alongside my local `myhdl' and of 
course the test is using this `myhdl`-tree, and I have a few experimental 
changes:
like instead of `if bool( sig ) then` I made toVHDL() output`if (sig = 
'1') then`. And the first test fails on that as it has this in the 
converted putput: ` a <= (not (a = '1'))(0);` where the unmodified myhdl 
would have produced ` a <= (not bool(a))(0);`, which I don't quite 
understand either. 

The main observation is that I'll have to set up that virtual Linux 
machine anyway.

Regards,

Josy

Re: [myhdl-list] Prerequisites to run the MyHDL regression test

[Christopher F. <chr...@gm...>]

<snip>
>
> Thanks for the hints and links.
> I downloaded git-bash and co, it came with *make*
> The core tests ran fine, one failure only.
> IVerilog is not well supported on Windows. As you know I not interested
> in Verilog, but I agree that I should be able to run the tests, if I
> start meddling with conversion etc. Maybe I'll set up that VirtualBox to
> run Linux one day, but my 250 GB SSD is running over ... The other
> alternative is to install the MingW complied version, but IIRC that's
> not straightforward either
> I have Altera's ModelSim ASE.
>

You should be fine with the Altera Modelsim then,
you can run the `make vcom`.  Are you able to run
`make vcom` with git-bash (you might have to add
the Altera path) in conversion/general?

Regards,
Chris

Re: [myhdl-list] Prerequisites to run the MyHDL regression test

[Josy B. <jos...@gm...>]

Christopher Felton <chris.felton <at> gmail.com> writes:
> 
> I do majority of my work on a *nix system.  I do have
> access to a Windows machine with Python and MyHDL setup.
> On this machine I use the git bash [1].  The git bash
> will have `make` etc. (I believe).  Then I also have
> `iverilog` and `modelsim`.  Some of the test require
> `py.test` [2] to be installed
> 
> The test suite has two categories:
> 
>     1. core (core and core2)
>     2. conversion
> 
> The *core* don't require any cosimulation, these you
> should be able to run out of the box.
> 
>     # setup myhdl, install the latest or create links
>     >> cd <clone dir>/myhdl/test/core
>     >> make
> 
> This will run one set of tests, you should see them
> all pass
> 
>     >> cd <clone dir>/myhdl/test/core2
>     >> py.test
> 
> This will run the second set of core tests, again
> all should pass.
> 
> For the conversion tests you will need a simulator
> installed an possibly the myhdl.vpi built and copied.
> The Windows machine I have access to, has modelsim.
> 
> To run the general conversion (these don't require
> the myhdl.vpi)
> 
>     >> cd <clone dir>myhdl/test/conversion/general
>     >> make vcom  # or make icarus, make GHDL, make vlog
> 
> On my linux machine, I have 3 failing tests on the master
> branch with `icarus` and 5 wiht `GHDL`.  On the windows
> machine I have most tests failing (icarus, GHDL, and VCOM)
> ... not sure why.  Is this what you are seeing (reporting)?
> 
> The toVerilog directories will require the myhdl.vpi, we
> can cover these in a follow-up.
> 
> [1] https://openhatch.org/missions/windows-setup/install-git-bashl
> [2] http://pytest.org/latest/getting-started.html
>
Chris,

Thanks for the hints and links.
I downloaded git-bash and co, it came with *make*
The core tests ran fine, one failure only.
IVerilog is not well supported on Windows. As you know I not interested 
in Verilog, but I agree that I should be able to run the tests, if I 
start meddling with conversion etc. Maybe I'll set up that VirtualBox to 
run Linux one day, but my 250 GB SSD is running over ... The other 
alternative is to install the MingW complied version, but IIRC that's 
not straightforward either
I have Altera's ModelSim ASE.

Regards,

Josy

Re: [myhdl-list] Prerequisites to run the MyHDL regression test

[Christopher F. <chr...@gm...>]

On 2/28/15 4:16 AM, Josy Boelen wrote:
> I happen to work under Windows (8.1) using PyDev, Sigasi VHDL editor and
> Impulse vcd-viewer plug-ins in Eclipse. It seems to me that most others
> work under Linux, though.
> What are the prerequisites to run the MyHDL regression tests? And can it
> be done under Windows? I tried some of them manually but all of them
> returned a lot of 'False' results.
>

I do majority of my work on a *nix system.  I do have
access to a Windows machine with Python and MyHDL setup.
On this machine I use the git bash [1].  The git bash
will have `make` etc. (I believe).  Then I also have
`iverilog` and `modelsim`.  Some of the test require
`py.test` [2] to be installed

The test suite has two categories:

    1. core (core and core2)
    2. conversion

The *core* don't require any cosimulation, these you
should be able to run out of the box.

    # setup myhdl, install the latest or create links
    >> cd <clone dir>/myhdl/test/core
    >> make

This will run one set of tests, you should see them
all pass

    >> cd <clone dir>/myhdl/test/core2
    >> py.test

This will run the second set of core tests, again
all should pass.

For the conversion tests you will need a simulator
installed an possibly the myhdl.vpi built and copied.
The Windows machine I have access to, has modelsim.

To run the general conversion (these don't require
the myhdl.vpi)

    >> cd <clone dir>myhdl/test/conversion/general
    >> make vcom  # or make icarus, make GHDL, make vlog

On my linux machine, I have 3 failing tests on the master
branch with `icarus` and 5 wiht `GHDL`.  On the windows
machine I have most tests failing (icarus, GHDL, and VCOM)
... not sure why.  Is this what you are seeing (reporting)?

The toVerilog directories will require the myhdl.vpi, we
can cover these in a follow-up.

[1] https://openhatch.org/missions/windows-setup/install-git-bashl
[2] http://pytest.org/latest/getting-started.html

[myhdl-list] Prerequisites to run the MyHDL regression test

[Josy B. <jos...@gm...>]

I happen to work under Windows (8.1) using PyDev, Sigasi VHDL editor and 
Impulse vcd-viewer plug-ins in Eclipse. It seems to me that most others 
work under Linux, though. 
What are the prerequisites to run the MyHDL regression tests? And can it 
be done under Windows? I tried some of them manually but all of them 
returned a lot of 'False' results. 

Regards,

Josy

Re: [myhdl-list] github & git questions

[Christopher F. <chr...@gm...>]

On 2/27/2015 9:52 AM, Edward Vidal wrote:
> Hello All,
> I just cloned gi...@gi...:jandecaluwe/myhdl.git
>   69c89fa70eb4ffc9da41e1ec449123fd6d6da6aa
>
>
> Did the following:
>      git checkout master
>      python setup.py install --home=$HOME
>      set the PYTHONPATH
>
> Should the generated header continue to be MyHDL 0.9dev or MyHDL 0.9?
>

I assume you are referring to the header in the
converted code?  If so, yes it should still be
0.9dev until the release.  If you clone and use
"master" it should always end in 'dev' (unless
something occurred that I am unaware of).

>
> Is the main development repo https://bitbucket.org/jandecaluwe/myhdl or github or both?

Github, the bitbucket repo has been retired.

<snip>

> Also should we fork or not?
> This is what I have been doing in the past

You only need to fork if you plan on contributing
changes, that is creating "pull requests".  If you
simply want to follow the most recent development
the clone (as you have done) is sufficient.

Regards,
Chris

[myhdl-list] github & git questions

[Edward V. <dev...@sb...>]

Hello All,
I just cloned gi...@gi...:jandecaluwe/myhdl.git
 69c89fa70eb4ffc9da41e1ec449123fd6d6da6aa


Did the following:
    git checkout master
    python setup.py install --home=$HOME
    set the PYTHONPATH 

Should the generated header continue to be MyHDL 0.9dev or MyHDL 0.9?


Is the main development repo https://bitbucket.org/jandecaluwe/myhdl or github or both?


I did notice that a change that Josy Boelen had provided me that limited the signals 
JP_PROCESS_JPEG_LOGIC: process (update_s, right_s(0), right_s(1), right_s(2), right_s(3), right_s(4), right_s(5), right_s(6), right_s(7), flgs_s(0), flgs_s(1), flgs_s(2), flgs_s(3), flgs_s(4), flgs_s(5), flgs_s(6), flgs_s(7), sam_s(0), sam_s(1), sam_s(2), sam_s(3), sam_s(4), sam_s(5), sam_s(6), sam_s(7), left_s(0), left_s(1), left_s(2), left_s(3), left_s(4), left_s(5), left_s(6), left_s(7)) is
to JP_PROCESS_JPEG_LOGIC: process (update_s, right_s, flgs_s, sam_s, left_s) is
was part of the new build.
Also should we fork or not?
This is what I have been doing in the past
 
At github fork the
repository.

clone locally.

git clone gi...@gi...:develone/meta-topic.git

git remote add
upstream git://github.com/topic-embedded-products/meta-topic.git

git fetch upstream

git merge
upstream/master

git push origin
master
If I don't make changes.  I check if the original owner has not made changes and if new changes
 
git fetch upstream

git merge
upstream/master

git push origin
master
Don't know if this is correct steps?

Just to new to know the process of changes and trying to understand?

Thanks for all the help    
     
    


 
Edward Vidal Jr.
e-mail dev...@sb...
915-595-1613

Re: [myhdl-list] written conversion filename?

[Henry G. <he...@ca...>]

On 27/02/15 15:12, Christopher Felton wrote:
> On 2/27/2015 8:48 AM, Henry Gomersall wrote:
>> >Am I correct in asserting that there is no way to directly get the
>> >converted filename from the results of e.g. toVHDL?
>> >
>> >It seems like this would be a useful thing to know for programmatic
>> >control of the outputs.
>> >
> Yes and no, after conversion you can't poll the
> toV*.filename and get the name of the recently
> created file.
>
> But, you can only pass a single top-level to the
> conversion functions, and this function can be
> queried for its name and simply append the
> extension.
>
>
> In [62]: def m_foobot(clock, reset, x, y):
>       ...:     @always_seq(clock.posedge, reset=reset)
>       ...:     def rtl():
>       ...:         x.next = y
>       ...:     return rtl
>       ...:
>
> In [63]: m_foobot.func_name
> Out[63]: 'm_foobot'

Unless toVHDL.name is set ;) (and also toVHDL.directory in dev)

Thanks, it confirms what I thought. That's not too onerous a work around.

Cheers,

Henry

Re: [myhdl-list] written conversion filename?

[Christopher F. <chr...@gm...>]

On 2/27/2015 8:48 AM, Henry Gomersall wrote:
> Am I correct in asserting that there is no way to directly get the
> converted filename from the results of e.g. toVHDL?
>
> It seems like this would be a useful thing to know for programmatic
> control of the outputs.
>

Yes and no, after conversion you can't poll the
toV*.filename and get the name of the recently
created file.

But, you can only pass a single top-level to the
conversion functions, and this function can be
queried for its name and simply append the
extension.


In [62]: def m_foobot(clock, reset, x, y):
     ...:     @always_seq(clock.posedge, reset=reset)
     ...:     def rtl():
     ...:         x.next = y
     ...:     return rtl
     ...:

In [63]: m_foobot.func_name
Out[63]: 'm_foobot'

In [64]:

Regards,
Chris

[myhdl-list] written conversion filename?

[Henry G. <he...@ca...>]

Am I correct in asserting that there is no way to directly get the 
converted filename from the results of e.g. toVHDL?

It seems like this would be a useful thing to know for programmatic 
control of the outputs.

Cheers,

Henry

[myhdl-list] Are we still using the old logo?

[Christopher F. <chr...@gm...>]

The new website doesn't incorporate the old logo,
(seems appropriate different color schemes).  Do
we still want to use the old logo?

Old logo
http://old.myhdl.org/doku.php/logo

Regards,
Chris

Re: [myhdl-list] MyHDL development has moved to git & GitHub

[Werner T. <we...@th...>]

Hi all

this seems to illustrate a good workflow quite nicely:

http://nvie.com/posts/a-successful-git-branching-model/

Werner

On 2/22/15 9:18 AM, Christopher Felton wrote:
> On 2/22/15 10:41 AM, Jan Decaluwe wrote:
>> On 02/22/2015 02:58 PM, Josy Boelen wrote:
>>> I suppose that we have to *fork* the repository first.
>>
>> Mm, a fork is just a clone that GitHub knows about.
>>
>> For tracking development, a local clone is sufficient.
>> No need to fork on GitHub first.
>>
>> To contribute changes, the guide mentions a fork on
>> GitHub, to be able to raise pull requests.
>>
>> Is this too confusing?
>
> No it is not too confusing, I think what exists is
> sufficient.  But I could see the addition of a recommend
> workflow using the personal github fork for contributions,
> example:
>
>      1. Fork on github
>
>      2. Clone the personal fork
>         >> git clone https://github.com/<username>/myhdl
>
>      3. Create a branch for the development enhancement
>         >> git checkout -b <branch name>
>
> I think the branch is important (??) because github only
> allows one fork whereas bitbucket-hg you would create many.
> If you start an enhancement and it is abandoned, the
> changes have to manually be unrolled vs. closing a branch
> and creating a new branch from the sync'd master branch.
>
>      4. To stay sync'd with the main repo add it as a
>         remote
>         >> git remote add <remote label> https://github.com/jandecaluwe/myhdl
>
>      5. Sync when necessarily
>         >> git fetch <remote label>
>
>      6. Make changes and push to personal fork, when
>         the changes are complete make sure the branch
>         is sync'd with the main repo and create a PR.
>
>
> I am still coming up to speed with git so the above
> could be complete malarkey!  And what I don't know,
> if branches are used for development, if the PR handles
> everything (merging) or if it manually has to be merged
> to the mainline (master) or should PRs always be to
> the main branch.
>
> Regards,
> Chris
>
>
>
>
> ------------------------------------------------------------------------------
> Download BIRT iHub F-Type - The Free Enterprise-Grade BIRT Server
> from Actuate! Instantly Supercharge Your Business Reports and Dashboards
> with Interactivity, Sharing, Native Excel Exports, App Integration & more
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> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>

Re: [myhdl-list] Is it time for 0.9 release?

[Jan D. <ja...@ja...>]

On 02/22/2015 08:09 PM, Christopher Felton wrote:
> On 2/22/15 3:14 AM, Jan Decaluwe wrote:
>> On 02/18/2015 08:16 AM, Keerthan JC wrote:
>>> Jan,
>>> Is it safe for me to fork your github repo and apply my commits on it
>>
>> Keerthan:
>>
>> We are on git/github now with an up-to-date repo and development
>> guide. Let's go ahead.
>>
>> Jan
>>
>
> Since we are going full speed with github, Keerthan
> should push the travis-CI scripts.  Can see the test
> results on the main repo page :)

I am sure he will but give the guy a break :-) (He has
to use some git magic to add unrelated commits to the repo.)


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] MyHDL development has moved to git & GitHub

[Colin B. <co...@sw...>]

What you've outlined is essentially our software dev process at Swift Nav,
Chris. What we do for merging PR's to master is that the PR should be a
fast forward on master, so if master has changed while you're working on
your dev branch, you're responsible for merging it into your dev branch
before creating your PR. This requires that PR's get reviewed and merged
quickly so there aren't multiple PR's sitting in the queue that touch the
same code, but this is probably something you want to be doing anyways.
ᐧ

On Sun, Feb 22, 2015 at 11:18 AM, Christopher Felton <chr...@gm...
> wrote:

> On 2/22/15 10:41 AM, Jan Decaluwe wrote:
> > On 02/22/2015 02:58 PM, Josy Boelen wrote:
> >> I suppose that we have to *fork* the repository first.
> >
> > Mm, a fork is just a clone that GitHub knows about.
> >
> > For tracking development, a local clone is sufficient.
> > No need to fork on GitHub first.
> >
> > To contribute changes, the guide mentions a fork on
> > GitHub, to be able to raise pull requests.
> >
> > Is this too confusing?
>
> No it is not too confusing, I think what exists is
> sufficient.  But I could see the addition of a recommend
> workflow using the personal github fork for contributions,
> example:
>
>     1. Fork on github
>
>     2. Clone the personal fork
>        >> git clone https://github.com/<username>/myhdl
>
>     3. Create a branch for the development enhancement
>        >> git checkout -b <branch name>
>
> I think the branch is important (??) because github only
> allows one fork whereas bitbucket-hg you would create many.
> If you start an enhancement and it is abandoned, the
> changes have to manually be unrolled vs. closing a branch
> and creating a new branch from the sync'd master branch.
>
>     4. To stay sync'd with the main repo add it as a
>        remote
>        >> git remote add <remote label>
> https://github.com/jandecaluwe/myhdl
>
>     5. Sync when necessarily
>        >> git fetch <remote label>
>
>     6. Make changes and push to personal fork, when
>        the changes are complete make sure the branch
>        is sync'd with the main repo and create a PR.
>
>
> I am still coming up to speed with git so the above
> could be complete malarkey!  And what I don't know,
> if branches are used for development, if the PR handles
> everything (merging) or if it manually has to be merged
> to the mainline (master) or should PRs always be to
> the main branch.
>
> Regards,
> Chris
>
>
>
>
>
> ------------------------------------------------------------------------------
> Download BIRT iHub F-Type - The Free Enterprise-Grade BIRT Server
> from Actuate! Instantly Supercharge Your Business Reports and Dashboards
> with Interactivity, Sharing, Native Excel Exports, App Integration & more
> Get technology previously reserved for billion-dollar corporations, FREE
>
> http://pubads.g.doubleclick.net/gampad/clk?id=190641631&iu=/4140/ostg.clktrk
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>

Re: [myhdl-list] MyHDL development has moved to git & GitHub

[Christopher F. <chr...@gm...>]

On 2/22/15 10:41 AM, Jan Decaluwe wrote:
> On 02/22/2015 02:58 PM, Josy Boelen wrote:
>> I suppose that we have to *fork* the repository first.
>
> Mm, a fork is just a clone that GitHub knows about.
>
> For tracking development, a local clone is sufficient.
> No need to fork on GitHub first.
>
> To contribute changes, the guide mentions a fork on
> GitHub, to be able to raise pull requests.
>
> Is this too confusing?

No it is not too confusing, I think what exists is
sufficient.  But I could see the addition of a recommend
workflow using the personal github fork for contributions,
example:

    1. Fork on github

    2. Clone the personal fork
       >> git clone https://github.com/<username>/myhdl

    3. Create a branch for the development enhancement
       >> git checkout -b <branch name>

I think the branch is important (??) because github only
allows one fork whereas bitbucket-hg you would create many.
If you start an enhancement and it is abandoned, the
changes have to manually be unrolled vs. closing a branch
and creating a new branch from the sync'd master branch.

    4. To stay sync'd with the main repo add it as a
       remote
       >> git remote add <remote label> https://github.com/jandecaluwe/myhdl

    5. Sync when necessarily
       >> git fetch <remote label>

    6. Make changes and push to personal fork, when
       the changes are complete make sure the branch
       is sync'd with the main repo and create a PR.


I am still coming up to speed with git so the above
could be complete malarkey!  And what I don't know,
if branches are used for development, if the PR handles
everything (merging) or if it manually has to be merged
to the mainline (master) or should PRs always be to
the main branch.

Regards,
Chris

Re: [myhdl-list] Is it time for 0.9 release?

[Christopher F. <chr...@gm...>]

On 2/22/15 3:14 AM, Jan Decaluwe wrote:
> On 02/18/2015 08:16 AM, Keerthan JC wrote:
>> Jan,
>> Is it safe for me to fork your github repo and apply my commits on it
>
> Keerthan:
>
> We are on git/github now with an up-to-date repo and development
> guide. Let's go ahead.
>
> Jan
>

Since we are going full speed with github, Keerthan
should push the travis-CI scripts.  Can see the test
results on the main repo page :)

Regards,
Chris

Re: [myhdl-list] MyHDL development has moved to git & GitHub

[Jan D. <ja...@ja...>]

On 02/22/2015 02:58 PM, Josy Boelen wrote:
> I suppose that we have to *fork* the repository first.

Mm, a fork is just a clone that GitHub knows about.

For tracking development, a local clone is sufficient.
No need to fork on GitHub first.

To contribute changes, the guide mentions a fork on
GitHub, to be able to raise pull requests.

Is this too confusing?


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] MyHDL development has moved to git & GitHub

[Jan D. <ja...@ja...>]

On 02/22/2015 03:23 PM, Josy Boelen wrote:
>
>>
>> The development guide has been updated accordingly:
>>
>>       http://dev.myhdl.org/guide.html
>
> The BugTracker link is blank(?). I suppose you mean
> *https://github.com/jandecaluwe/myhdl/issues*

Indeed. Should be fixed, thanks.


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] MyHDL development has moved to git & GitHub

[Jan D. <ja...@ja...>]

On 02/22/2015 02:49 PM, Josy Boelen wrote:
> Jan Decaluwe <jan <at> jandecaluwe.com> writes:
>
>>
>> Hello:
>>
>> MyHDL development has moved to git & GitHub.
>>
>> The development guide has been updated accordingly:
>>
>>       http://dev.myhdl.org/guide.html
>>
>> <snip>
>
> the link on the http://dev.myhdl.org/guide.html page specifies
> github.*org* (which doesn't exist) in stead of than github.*com*

Yes, this was still wrong for the repo. Thanks.


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com