myhdl-list — Mailing list for discussions on MyHDL

[myhdl-list] use constants as signals

[Katrin W. <kat...@s2...>]

Hello,

I need to declare a signal with a constant value at the beginning of  
my program. This signal is needed in an always_comb decorator in  
another function, where it is changed.

There is a problem with the conversion to VHDL, because in VHDL you  
can not declare a signal with a constant value at the beginning of a  
program.
So I've tried to assign the value to the signal in a always_comb  
decorator, but the input signal doesn't change and the always_comb  
decorator is not called.
There is also a problem, if I declare an intbv variable of this  
constant value, because the always_comb decorator can not change intbv  
variables.
Does anybody know a solution to my problem?

I've attached two examples of my problem.

best regards

Katrin

#####################################

def foo1():
   a = Signal(intbv(12)[8:])

   @always_comb
   def bar():
     a.next = 12 # not working because sensitivity list is empty

def foo2():
   a = intbv(12)[8:]

   @always_comb
   def bar():
     b.next = a >> 1 # always_comb cannot handle intbv constants

Re: [myhdl-list] elif + toVHDL function

[Patrick <pat...@gm...>]

Thank you for your quick reply and for the link.
I haven't used VHDL in a while and I didn't stop to think about the
difference between verilog/VHDL sensitivity lists.

Thanks,
Patrick

On Mon, Mar 29, 2010 at 3:15 PM, Jan Decaluwe <ja...@ja...> wrote:

> patrick wrote:
>
> >
> > I have a question on myHDL's conversion capabilities:
> > When I use a 'elif some_condition:' statement and try to translate it
> > to VHDL I get the following error:
> >
> > myhdl.ConversionError: in file regp2p.py, line 15:
> >     no else test
> >
> > With the toVerilog function the translation works fine.
> >
> > Is a 'elif some_condition:' statement treated differently by the
> > toVHDL function (than by the toVerilog function) or is a 'elif
> > some_condition:' statement in myHDL something other than a 'else: if
> > some_condition:' statement?
>
> The basic issue is explained here:
>
> http://www.myhdl.org/doc/0.6/whatsnew/0.6.html#template-transformation
>
> It may be possible to make template transformation more
> sophisticated and handle code such as yours. However, the
> workaround for now is to put the clock-triggered part of
> the logic in the "else" clause, as you found out.
>
> Jan
>
> --
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
>    Python as a HDL: http://www.myhdl.org
>    VHDL development, the modern way: http://www.sigasi.com
>    Analog design automation: http://www.mephisto-da.com
>    World-class digital design: http://www.easics.com
>
>
>
> ------------------------------------------------------------------------------
> Download Intel&#174; Parallel Studio Eval
> Try the new software tools for yourself. Speed compiling, find bugs
> proactively, and fine-tune applications for parallel performance.
> See why Intel Parallel Studio got high marks during beta.
> http://p.sf.net/sfu/intel-sw-dev
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>

Re: [myhdl-list] elif + toVHDL function

[Jan D. <ja...@ja...>]

patrick wrote:

> 
> I have a question on myHDL's conversion capabilities:
> When I use a 'elif some_condition:' statement and try to translate it
> to VHDL I get the following error:
> 
> myhdl.ConversionError: in file regp2p.py, line 15:
>     no else test
> 
> With the toVerilog function the translation works fine.
> 
> Is a 'elif some_condition:' statement treated differently by the
> toVHDL function (than by the toVerilog function) or is a 'elif
> some_condition:' statement in myHDL something other than a 'else: if
> some_condition:' statement?

The basic issue is explained here:

http://www.myhdl.org/doc/0.6/whatsnew/0.6.html#template-transformation

It may be possible to make template transformation more
sophisticated and handle code such as yours. However, the
workaround for now is to put the clock-triggered part of
the logic in the "else" clause, as you found out.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

[myhdl-list] elif + toVHDL function

[patrick <pat...@gm...>]

Hello everyone,

this is my first post to this list. I also posted this question on 
comp.lang.verilog and comp.lang.vhdl as a 'reply' to the message on the 
first ASIC designed with myHDL (great news!).
This list is probably more appropriate for posting my question, so here 
goes. The rest of this message is a copy of the text also posted to the 
newsgroups:

Hello Jan,

First of all, congratulations with this result!

I have only recently become acquainted with myHDL and it looks very
nice.
Specifically, I like myHDL's conversion capabilities and the
possibility of writing testbenches in python.

I have a question on myHDL's conversion capabilities:
When I use a 'elif some_condition:' statement and try to translate it
to VHDL I get the following error:

myhdl.ConversionError: in file regp2p.py, line 15:
    no else test

With the toVerilog function the translation works fine.

Is a 'elif some_condition:' statement treated differently by the
toVHDL function (than by the toVerilog function) or is a 'elif
some_condition:' statement in myHDL something other than a 'else: if
some_condition:' statement?

I attached a small example at the end of this post (a posedge
sensitive register with an asynchronous clear and an enable input).

Thanks,
Patrick

from myhdl import *

def regp2p(
           clr,
           clk,
           en,
           pin,
           pout,
           width
          ):

   intreg = Signal(intbv(0)[width:])

   @always(clk.posedge, clr.posedge)
   def register_p2p():
      if clr:
         intreg.next = 0
# This works with toVerilog but not with toVHDL
      elif en:
         intreg.next = pin
# This works with both toVerilog and toVHDL
#      else:
#         if en:
#            intreg.next = pin

   @always_comb
   def outputs():
      pout.next = intreg

   return register_p2p, outputs

width = int(8)
clr   = Signal(bool(0))
clk   = Signal(bool(0))
en    = Signal(bool(0))
pin   = Signal(intbv(0)[width:])
pout  = Signal(intbv(0)[width:])

def main():
    toVerilog.name = 'regp2p'
    toVerilog(
              regp2p,
              clr    = clr,
              clk    = clk,
              en     = en,
              pin    = pin,
              pout   = pout,
              width  = width
             )
    toVHDL(
           regp2p,
           clr    = clr,
           clk    = clk,
           en     = en,
           pin    = pin,
           pout   = pout,
           width  = width
          )

if __name__ == '__main__':
    main()

[myhdl-list] The first ASIC designed with MyHDL

[Jan D. <ja...@ja...>]

http://www.jandecaluwe.com/hdldesign/digmac.html

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

[myhdl-list] MyHDL on Ubuntu

[Jan D. <ja...@ja...>]

http://balau82.wordpress.com/2010/02/23/myhdl-on-ubuntu/

(Thanks to Francesco Balducci)

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

Re: [myhdl-list] Xilinx ISE and MyHDL

[Jan D. <ja...@ja...>]

Jan Decaluwe wrote:
> Mike Gill wrote:
>> Jan Decaluwe <jan <at> jandecaluwe.com> writes:
>>
>>> Mike Gill wrote:
>>>> Hi,
>>>>
>>>> It is very attractive for the entire source code for a Xilinx ISE project 
>> to be 
>>>> managed in Python via myHDL. This needs Xilinx chip features like clock 
>>>> generators and RAM to be defined in Python. Is this possible, and what is 
>> the 
>>>> best approach?
>>> In many cases, RAMs can be inferred from technology-independent
>>> RTL code, which is the preferred approach if it works.
>>>
>>> To instantiate technology-specific modules, you can use the
>>> __verilog__ or __vhdl__ hook. For simulation purposes,
>>> describe the functionality as usual. The convertor
>>> will ignore that code and use the appopriate hook if it exists.
>>>
>>> See:
>>>
>>> http://www.myhdl.org/doc/0.6/manual/conversion.html#user-defined-code
>>>
>> Thanks for reply
>>
>> Making ROM and distributed RAM is easy, but so far no luck with block RAM, and 
>> am afraid I can't work out from the manual section "User-Defined code" if and 
>> how to include a complete VHDL module such as made by an ISE wizard, or whether 
>> the code has to be copied and pasted, and in which case what (I am hoping MyHDL 
>> means not having to learn VHDL or Verilog in any detail)
> 
> The only thing what you have to include is the VHDL or Verilog instantation of
> the module. (The part about instantiation in VHDL or Verilog, you'll have to learn).
> 
> When your have made a macro, think about how you would instantiate that in
> another Verilog or VHDL design. Paste such an instantiation into a string
> assigned to __vhdl__ or __verilog__ in your MyHDL code.
> 
> The remaining thing is the way to attach MyHDL signals to the ports in your
> instantiation. Instead of having actual Verilog or VHDL signal names in your
> instantiation, you use Python format strings referring to MyHDL signals. E.g.
> instead of "clock" you would use "%(clock). (I think this should be clear from
> the examples, even though they don't show instantiations.)
> 
> Now after conversion, your code would contain the instantiation with the 
> appropriate signals names filled in by the convertor.
> 
> Hope this helps?

Let me add to my reply above that I was answering your question related
to user-defined code. I didn't intend to advocate that approach, certainly
not in this case.

As others have pointed out, I don't think user-defined code is the best option
for block ram. Back end tools should be able to infer that from a
technology-independent description.

Personally I would limit user-defined code for those cases were inference
by a synthesis tool or other back-end tools really isn't possible.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

Re: [myhdl-list] Xilinx ISE and MyHDL

[Jan D. <ja...@ja...>]

Mike Gill wrote:
> Jan Decaluwe <jan <at> jandecaluwe.com> writes:
> 
>> Mike Gill wrote:
>>> Hi,
>>>
>>> It is very attractive for the entire source code for a Xilinx ISE project 
> to be 
>>> managed in Python via myHDL. This needs Xilinx chip features like clock 
>>> generators and RAM to be defined in Python. Is this possible, and what is 
> the 
>>> best approach?
>> In many cases, RAMs can be inferred from technology-independent
>> RTL code, which is the preferred approach if it works.
>>
>> To instantiate technology-specific modules, you can use the
>> __verilog__ or __vhdl__ hook. For simulation purposes,
>> describe the functionality as usual. The convertor
>> will ignore that code and use the appopriate hook if it exists.
>>
>> See:
>>
>> http://www.myhdl.org/doc/0.6/manual/conversion.html#user-defined-code
>>
> 
> Thanks for reply
> 
> Making ROM and distributed RAM is easy, but so far no luck with block RAM, and 
> am afraid I can't work out from the manual section "User-Defined code" if and 
> how to include a complete VHDL module such as made by an ISE wizard, or whether 
> the code has to be copied and pasted, and in which case what (I am hoping MyHDL 
> means not having to learn VHDL or Verilog in any detail)

The only thing what you have to include is the VHDL or Verilog instantation of
the module. (The part about instantiation in VHDL or Verilog, you'll have to learn).

When your have made a macro, think about how you would instantiate that in
another Verilog or VHDL design. Paste such an instantiation into a string
assigned to __vhdl__ or __verilog__ in your MyHDL code.

The remaining thing is the way to attach MyHDL signals to the ports in your
instantiation. Instead of having actual Verilog or VHDL signal names in your
instantiation, you use Python format strings referring to MyHDL signals. E.g.
instead of "clock" you would use "%(clock). (I think this should be clear from
the examples, even though they don't show instantiations.)

Now after conversion, your code would contain the instantiation with the 
appropriate signals names filled in by the convertor.

Hope this helps?


> I'd be grateful for an example. You seem to have a preference for Verilog - is 
> this true?

Certainly not :-)

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

Re: [myhdl-list] Xilinx ISE and MyHDL

[Christopher F. <chr...@gm...>]

Cross, posts, yes I can generate BRAM with ISE and Synplicity.  My
observations is the Synthesis tool (and map can modify) will determine based
on the size and routing which to use DRAM or BRAM.  If you wanted to force
the use of BRAM that might be a different issue.  But I think the question
can be asked, why force to BRAM?

.chris

On Mon, Feb 22, 2010 at 10:30 AM, Kevin Stanton <sta...@gm...> wrote:

> I am surprised you can't get Xilinx ISE to instantiate Block RAM.  I am
> very, very new to MyHDL and haven't done much yet other than follow the
> tutorials, but I come from a strong VHDL background and have used all the
> big FPGA vendors in projects: Xilinx, Altera, and Actel.
>
> I have no problem getting Xilinx ISE to instantiate block ram with VHDL
> code as simple as:
>
> -- declaration of fifoMem
> type FifoMemType is array(0 to DEPTH-1) of std_logic_vector(dataW'range);
> signal fifoMem : FifoMemType;
>
> -- code snippet of usage of fifoMem
> process (clkW)
> begin
>   if (rising_edge(clkW)) then
>     if (rstW = '1') then
>       fifoMem <= (others => (others => '0'));
>     else
>       if (we = '1' and full = '0') then
>         fifoMem(conv_integer(addrW'length-2 downto 0))) <= dataW;
>       end if;
>     end if;
>   end if;
> end process;
>
> -- do something similar for a read.
>
> So, you see, you can't just create an array of std_logic_vectors, and your
> synthesis tool should pick out a Block RAM.  I use Synplify Pro (not XST) so
> it is possible XST isn't as capable, but Synplify Pro seems to have no
> problem mapping block ram to an RTL implementation of an async FIFO.
>
> I would think that a MyHDL implementation of something similar should
> produce synthesizable VHDL or Verilog that would properly map to a Block RAM
> upon elaboration.
>
> Can anyone with more MyHDL experience corroborate this?  If you could write
> a working memory in MyHDL I could try synthesizing it in Synplify Pro to see
> what happens...
>
> Kevin
>
>
> On Mon, Feb 22, 2010 at 9:42 AM, Mike Gill <zen...@ze...> wrote:
>
>> Jan Decaluwe <jan <at> jandecaluwe.com> writes:
>>
>> >
>> > Mike Gill wrote:
>> > > Hi,
>> > >
>> > > It is very attractive for the entire source code for a Xilinx ISE
>> project
>> to be
>> > > managed in Python via myHDL. This needs Xilinx chip features like
>> clock
>> > > generators and RAM to be defined in Python. Is this possible, and what
>> is
>> the
>> > > best approach?
>> >
>> > In many cases, RAMs can be inferred from technology-independent
>> > RTL code, which is the preferred approach if it works.
>> >
>> > To instantiate technology-specific modules, you can use the
>> > __verilog__ or __vhdl__ hook. For simulation purposes,
>> > describe the functionality as usual. The convertor
>> > will ignore that code and use the appopriate hook if it exists.
>> >
>> > See:
>> >
>> > http://www.myhdl.org/doc/0.6/manual/conversion.html#user-defined-code
>> >
>>
>> Thanks for reply
>>
>> Making ROM and distributed RAM is easy, but so far no luck with block RAM,
>> and
>> am afraid I can't work out from the manual section "User-Defined code" if
>> and
>> how to include a complete VHDL module such as made by an ISE wizard, or
>> whether
>> the code has to be copied and pasted, and in which case what (I am hoping
>> MyHDL
>> means not having to learn VHDL or Verilog in any detail)
>>
>> I'd be grateful for an example. You seem to have a preference for Verilog
>> - is
>> this true?
>>
>> MyHDL is a terrific idea, as is Python itself, but not many people are
>> willing
>> to strain their brains with new ideas, and need a lot of help and
>> encouragement. How to use MyHDL in the design flow would help a lot, and
>> examples of complete projects. DLP Design make a low cost Xilinx fpga
>> module
>> that is good for training, and it is easy to re-base their example
>> projects on
>> MyHDL (and talk to the module with a Python GUI)
>>
>> The "flat" Verilog or VHDL file output means the ISE schematic has no
>> useful
>> hierarchy for complete designs. I find myself converting/synthesising
>> individual blocks to see what each looks like, before assembling the whole
>> design. MyHDL is a very fast approach and complicated stuff can be put
>> together
>> very quickly.
>>
>> Regards
>>
>> Mike
>>
>>
>>
>>
>>
>> ------------------------------------------------------------------------------
>> Download Intel&#174; Parallel Studio Eval
>> Try the new software tools for yourself. Speed compiling, find bugs
>> proactively, and fine-tune applications for parallel performance.
>> See why Intel Parallel Studio got high marks during beta.
>> http://p.sf.net/sfu/intel-sw-dev
>> _______________________________________________
>> myhdl-list mailing list
>> myh...@li...
>> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>
>
>
>
> --
> Kevin R. Stanton
> c | 734•846•3915
> e | sta...@gm...
>
>
> ------------------------------------------------------------------------------
> Download Intel&#174; Parallel Studio Eval
> Try the new software tools for yourself. Speed compiling, find bugs
> proactively, and fine-tune applications for parallel performance.
> See why Intel Parallel Studio got high marks during beta.
> http://p.sf.net/sfu/intel-sw-dev
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>
>

Re: [myhdl-list] Xilinx ISE and MyHDL

[Christopher F. <cf...@uc...>]

On Mon, Feb 22, 2010 at 9:42 AM, Mike Gill <zen...@ze...> wrote:

> Jan Decaluwe <jan <at> jandecaluwe.com> writes:
>
> >
> > Mike Gill wrote:
> > > Hi,
> > >
> > > It is very attractive for the entire source code for a Xilinx ISE
> project
> to be
> > > managed in Python via myHDL. This needs Xilinx chip features like clock
> > > generators and RAM to be defined in Python. Is this possible, and what
> is
> the
> > > best approach?
> >
> > In many cases, RAMs can be inferred from technology-independent
> > RTL code, which is the preferred approach if it works.
> >
> > To instantiate technology-specific modules, you can use the
> > __verilog__ or __vhdl__ hook. For simulation purposes,
> > describe the functionality as usual. The convertor
> > will ignore that code and use the appopriate hook if it exists.
> >
> > See:
> >
> > http://www.myhdl.org/doc/0.6/manual/conversion.html#user-defined-code
> >
>
> Thanks for reply
>
> Making ROM and distributed RAM is easy, but so far no luck with block RAM,
> and
>

I think you will find that XST will determine, based on size, which to use
distributed or BRAM.  I have successfully inferred BRAM using the methods
Jan described.


> am afraid I can't work out from the manual section "User-Defined code" if
> and
> how to include a complete VHDL module such as made by an ISE wizard, or
> whether
> the code has to be copied and pasted, and in which case what (I am hoping
> MyHDL
> means not having to learn VHDL or Verilog in any detail)
>
> I'd be grateful for an example. You seem to have a preference for Verilog -
> is
> this true?
>

I don't think there is a preference for Verilog.  MyHDL is agnostic to which
HDL you convert to.  Many of the examples might be in Verilog because
Verilog was implemented first.  MyHDL was influenced by VHDL more than
Verilog.


>
> MyHDL is a terrific idea, as is Python itself, but not many people are
> willing
> to strain their brains with new ideas, and need a lot of help and
> encouragement. How to use MyHDL in the design flow would help a lot, and
> examples of complete projects. DLP Design make a low cost Xilinx fpga
> module
> that is good for training, and it is easy to re-base their example projects
> on
> MyHDL (and talk to the module with a Python GUI)
>

In the user and project areas there are many examples and projects.  If a
particular project or example is not clear or seems limited I think you will
get fast response if you post a specific questions to this mail group.  Me
personally, I use a top-level (very small) HDL (VHDL or Verilog)
to instantiate all vendor-hardware specific modules (
http://www.myhdl.org/doku.php/users:cfelton:projects:usbp).  I don't see any
drawback to this, all my work/development is in MyHDL.  All my simulation is
done with the MyHDL top-level.  I have had good success with MyHDL using a
variety of FPGA vendors.


>
> The "flat" Verilog or VHDL file output means the ISE schematic has no
> useful
> hierarchy for complete designs. I find myself converting/synthesising
> individual blocks to see what each looks like, before assembling the whole
> design. MyHDL is a very fast approach and complicated stuff can be put
> together
> very quickly.
>

Hmmm, not sure if you think this is a problem or it just an observation?


>
> Regards
>
> Mike
>
>
>
>
>
> ------------------------------------------------------------------------------
> Download Intel&#174; Parallel Studio Eval
> Try the new software tools for yourself. Speed compiling, find bugs
> proactively, and fine-tune applications for parallel performance.
> See why Intel Parallel Studio got high marks during beta.
> http://p.sf.net/sfu/intel-sw-dev
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>

Re: [myhdl-list] Xilinx ISE and MyHDL

[Kevin S. <sta...@gm...>]

I am surprised you can't get Xilinx ISE to instantiate Block RAM.  I am
very, very new to MyHDL and haven't done much yet other than follow the
tutorials, but I come from a strong VHDL background and have used all the
big FPGA vendors in projects: Xilinx, Altera, and Actel.

I have no problem getting Xilinx ISE to instantiate block ram with VHDL code
as simple as:

-- declaration of fifoMem
type FifoMemType is array(0 to DEPTH-1) of std_logic_vector(dataW'range);
signal fifoMem : FifoMemType;

-- code snippet of usage of fifoMem
process (clkW)
begin
  if (rising_edge(clkW)) then
    if (rstW = '1') then
      fifoMem <= (others => (others => '0'));
    else
      if (we = '1' and full = '0') then
        fifoMem(conv_integer(addrW'length-2 downto 0))) <= dataW;
      end if;
    end if;
  end if;
end process;

-- do something similar for a read.

So, you see, you can't just create an array of std_logic_vectors, and your
synthesis tool should pick out a Block RAM.  I use Synplify Pro (not XST) so
it is possible XST isn't as capable, but Synplify Pro seems to have no
problem mapping block ram to an RTL implementation of an async FIFO.

I would think that a MyHDL implementation of something similar should
produce synthesizable VHDL or Verilog that would properly map to a Block RAM
upon elaboration.

Can anyone with more MyHDL experience corroborate this?  If you could write
a working memory in MyHDL I could try synthesizing it in Synplify Pro to see
what happens...

Kevin

On Mon, Feb 22, 2010 at 9:42 AM, Mike Gill <zen...@ze...> wrote:

> Jan Decaluwe <jan <at> jandecaluwe.com> writes:
>
> >
> > Mike Gill wrote:
> > > Hi,
> > >
> > > It is very attractive for the entire source code for a Xilinx ISE
> project
> to be
> > > managed in Python via myHDL. This needs Xilinx chip features like clock
> > > generators and RAM to be defined in Python. Is this possible, and what
> is
> the
> > > best approach?
> >
> > In many cases, RAMs can be inferred from technology-independent
> > RTL code, which is the preferred approach if it works.
> >
> > To instantiate technology-specific modules, you can use the
> > __verilog__ or __vhdl__ hook. For simulation purposes,
> > describe the functionality as usual. The convertor
> > will ignore that code and use the appopriate hook if it exists.
> >
> > See:
> >
> > http://www.myhdl.org/doc/0.6/manual/conversion.html#user-defined-code
> >
>
> Thanks for reply
>
> Making ROM and distributed RAM is easy, but so far no luck with block RAM,
> and
> am afraid I can't work out from the manual section "User-Defined code" if
> and
> how to include a complete VHDL module such as made by an ISE wizard, or
> whether
> the code has to be copied and pasted, and in which case what (I am hoping
> MyHDL
> means not having to learn VHDL or Verilog in any detail)
>
> I'd be grateful for an example. You seem to have a preference for Verilog -
> is
> this true?
>
> MyHDL is a terrific idea, as is Python itself, but not many people are
> willing
> to strain their brains with new ideas, and need a lot of help and
> encouragement. How to use MyHDL in the design flow would help a lot, and
> examples of complete projects. DLP Design make a low cost Xilinx fpga
> module
> that is good for training, and it is easy to re-base their example projects
> on
> MyHDL (and talk to the module with a Python GUI)
>
> The "flat" Verilog or VHDL file output means the ISE schematic has no
> useful
> hierarchy for complete designs. I find myself converting/synthesising
> individual blocks to see what each looks like, before assembling the whole
> design. MyHDL is a very fast approach and complicated stuff can be put
> together
> very quickly.
>
> Regards
>
> Mike
>
>
>
>
>
> ------------------------------------------------------------------------------
> Download Intel&#174; Parallel Studio Eval
> Try the new software tools for yourself. Speed compiling, find bugs
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c | 734•846•3915
e | sta...@gm...

Re: [myhdl-list] Xilinx ISE and MyHDL

[Mike G. <zen...@ze...>]

Jan Decaluwe <jan <at> jandecaluwe.com> writes:

> 
> Mike Gill wrote:
> > Hi,
> > 
> > It is very attractive for the entire source code for a Xilinx ISE project 
to be 
> > managed in Python via myHDL. This needs Xilinx chip features like clock 
> > generators and RAM to be defined in Python. Is this possible, and what is 
the 
> > best approach?
> 
> In many cases, RAMs can be inferred from technology-independent
> RTL code, which is the preferred approach if it works.
> 
> To instantiate technology-specific modules, you can use the
> __verilog__ or __vhdl__ hook. For simulation purposes,
> describe the functionality as usual. The convertor
> will ignore that code and use the appopriate hook if it exists.
> 
> See:
> 
> http://www.myhdl.org/doc/0.6/manual/conversion.html#user-defined-code
> 

Thanks for reply

Making ROM and distributed RAM is easy, but so far no luck with block RAM, and 
am afraid I can't work out from the manual section "User-Defined code" if and 
how to include a complete VHDL module such as made by an ISE wizard, or whether 
the code has to be copied and pasted, and in which case what (I am hoping MyHDL 
means not having to learn VHDL or Verilog in any detail)

I'd be grateful for an example. You seem to have a preference for Verilog - is 
this true?

MyHDL is a terrific idea, as is Python itself, but not many people are willing 
to strain their brains with new ideas, and need a lot of help and 
encouragement. How to use MyHDL in the design flow would help a lot, and 
examples of complete projects. DLP Design make a low cost Xilinx fpga module 
that is good for training, and it is easy to re-base their example projects on 
MyHDL (and talk to the module with a Python GUI)

The "flat" Verilog or VHDL file output means the ISE schematic has no useful 
hierarchy for complete designs. I find myself converting/synthesising 
individual blocks to see what each looks like, before assembling the whole 
design. MyHDL is a very fast approach and complicated stuff can be put together 
very quickly.

Regards

Mike

Re: [myhdl-list] Xilinx ISE and MyHDL

[Jan D. <ja...@ja...>]

Mike Gill wrote:
> Hi,
> 
> It is very attractive for the entire source code for a Xilinx ISE project to be 
> managed in Python via myHDL. This needs Xilinx chip features like clock 
> generators and RAM to be defined in Python. Is this possible, and what is the 
> best approach?

In many cases, RAMs can be inferred from technology-independent
RTL code, which is the preferred approach if it works.

To instantiate technology-specific modules, you can use the
__verilog__ or __vhdl__ hook. For simulation purposes,
describe the functionality as usual. The convertor
will ignore that code and use the appopriate hook if it exists.

See:

http://www.myhdl.org/doc/0.6/manual/conversion.html#user-defined-code

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

Re: [myhdl-list] fixed_point library and VHDL generation

[Jan L. <jan...@et...>]

Am 15.01.2010 um 09:31 schrieb Jan Decaluwe:
> Jan Langer wrote:
>> The second thing I want to share were two issues during VHDL  
>> synthesis.
>> First, the assignments of constants of bit lengths greater 32 does  
>> not
>> work. I will append a patch for that, that uses bit strings in this  
>> case.
>
> The convertor has some provisions to handle this type of problems,
> please let me know where it still goes wrong.


Hello Jan,
I think it still goes wrong. Just checked with the current repository.
Jan

-- 
Jan Langer
(Tel) +49-371-531-33158 / (PGP) F1B8C1CC
Schaltkreis- und Systementwurf / TU Chemnitz

[myhdl-list] Xilinx ISE and MyHDL

[Mike G. <zen...@ze...>]

Hi,

It is very attractive for the entire source code for a Xilinx ISE project to be 
managed in Python via myHDL. This needs Xilinx chip features like clock 
generators and RAM to be defined in Python. Is this possible, and what is the 
best approach?


Many thanks

Mike

Re: [myhdl-list] verilog conversion issue (discrepancy between Python2.5 and 2.6)

[Jose I. V. <jo...@dt...>]

Hi,
there are two versions of this core:

using external ram at the ldc display:
http://www.opencores.org/websvn,filedetails?repname=wb_lcd&path=%2Fwb_lcd%2Ftrunk%2Fmyhdl%2Fwb_lcd_workspace_ramless%2Fworkspace%2Flcd_display%2Fsrc%2Flcd_display.py

using an internal ram block to store display contents (quicker and bigger):
http://www.opencores.org/websvn,filedetails?repname=wb_lcd&path=%2Fwb_lcd%2Ftrunk%2Fmyhdl%2Fwb_lcd_workspace%2Fworkspace%2Flcd_display%2Fsrc%2Flcd_display.py


José Ignacio Villar <jo...@dt...>
Departamento de Tecnología Electrónica
Escuela Técnica Superior de Ingeniería Informática
Universidad de Sevilla
Avda. Reina Mercedes, s/n
41012 - Sevilla (Spain)

Tlf: 954 55 99 62
Fax: 954 55 27 64



On Wed, Feb 10, 2010 at 1:03 AM, Jan Decaluwe <ja...@ja...> wrote:

> Jose Ignacio Villar wrote:
> > Hi all,
> > some time ago i developed an lcd controller using Myhdl 0.6 and Python
> > 2.5 that can be found on opencores
> > (http://www.opencores.org/project,wb_lcd).
>
> I was trying to browse through your myhdl code in the
> svn browser, but I don't seem to find it, can
> you tell me were it is?
>
> Thanks
>
> Jan
>
>
>
> --
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
>    Python as a HDL: http://www.myhdl.org
>    VHDL development, the modern way: http://www.sigasi.com
>    Analog design automation: http://www.mephisto-da.com
>    World-class digital design: http://www.easics.com
>
>
>
> ------------------------------------------------------------------------------
> SOLARIS 10 is the OS for Data Centers - provides features such as DTrace,
> Predictive Self Healing and Award Winning ZFS. Get Solaris 10 NOW
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> _______________________________________________
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> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>

Re: [myhdl-list] verilog conversion issue (discrepancy between Python2.5 and 2.6)

[Jan D. <ja...@ja...>]

Jose Ignacio Villar wrote:
> Hi all,
> some time ago i developed an lcd controller using Myhdl 0.6 and Python 
> 2.5 that can be found on opencores 
> (http://www.opencores.org/project,wb_lcd).

I was trying to browse through your myhdl code in the
svn browser, but I don't seem to find it, can
you tell me were it is?

Thanks

Jan



-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

Re: [myhdl-list] verilog conversion issue (discrepancy between Python2.5 and 2.6)

[Jose I. V. <jo...@dt...>]

Hello again,

It seems that it was being caused by some strange problem with my Python
installation, after purging the python packages and installing them again
the error has stopped appearing.

I can't recover the traceback now that I was not able to reproduce the
failure after reinstall, but it was related to the visitName method at class
_ConvertVisitor from the Verilog converter.
Instead of an EnumItemType the method was getting an EnumType, so it was
jumping over line 872 [elif isinstance(obj, EnumItemType):] and it was
throwing the error at line 876 in _toVerilog.py [ self.raiseError(node,
_error.UnsupportedType, "%s, %s" % (n, type(obj))) ]


Thanks for your help!

Regards, Jose.

José Ignacio Villar <jo...@dt...>
Departamento de Tecnología Electrónica
Escuela Técnica Superior de Ingeniería Informática
Universidad de Sevilla
Avda. Reina Mercedes, s/n
41012 - Sevilla (Spain)

Tlf: 954 55 99 62
Fax: 954 55 27 64



On Tue, Feb 9, 2010 at 3:15 PM, Jan Decaluwe <ja...@ja...> wrote:

> Could you show the error messages?
>
> Both options seem to work for me.
>
> Jan
>
> Jose Ignacio Villar wrote:
> > Hi all,
> > some time ago i developed an lcd controller using Myhdl 0.6 and Python
> > 2.5 that can be found on opencores
> > (http://www.opencores.org/project,wb_lcd).
> >
> > This week I updated my system to Python 2.6 and bleeding edge branch of
> > Myhdl. But when I tried to convert it to Verilog it started shouting
> > because of some lines that were already working with Python 2.5.
> >
> > The problem is about the following kind of generators:
> >
> >     @always_comb
> >     def output_tx_or_init_select():
> >         testOut.next = (state == t_State.SEARCH) | (state ==
> > t_State.CONFIRM)
> >
> > that in Python 2.6 used to generate the following verilog code:
> >
> > assign testOut = ((state == 3'b001) | (state == 3'b010));
> >
> > Everything fixed up by changing "|" operator by an Python "or":
> >
> >     @always_comb
> >     def output_tx_or_init_select():
> >         testOut.next = (state == t_State.SEARCH) or (state ==
> > t_State.CONFIRM)
> >
> > and now it generates:
> >
> > assign testOut = ((state == 3'b001) || (state == 3'b010));
> >
> > Although both are working in my fpga, and from the verilog point of view
> > (If I'm not mistaken) are functionally equivalent, should Python 2.6 be
> > able to extract correct code for the first approach?
> > I'd like to hear what experts think about it before spending several
> > days digging in the code to find taht I was wrong.
> >
> > Kind Regards,
> > Jose Ignacio Villar.
> >
> > José Ignacio Villar <jo...@dt... <mailto:jo...@dt...>>
> > Departamento de Tecnología Electrónica
> > Escuela Técnica Superior de Ingeniería Informática
> > Universidad de Sevilla
> > Avda. Reina Mercedes, s/n
> > 41012 - Sevilla (Spain)
> >
> > Tlf: 954 55 99 62
> > Fax: 954 55 27 64
> >
> >
> > ------------------------------------------------------------------------
> >
> >
> ------------------------------------------------------------------------------
> > The Planet: dedicated and managed hosting, cloud storage, colocation
> > Stay online with enterprise data centers and the best network in the
> business
> > Choose flexible plans and management services without long-term contracts
> > Personal 24x7 support from experience hosting pros just a phone call
> away.
> > http://p.sf.net/sfu/theplanet-com
> >
> >
> > ------------------------------------------------------------------------
> >
> > _______________________________________________
> > myhdl-list mailing list
> > myh...@li...
> > https://lists.sourceforge.net/lists/listinfo/myhdl-list
>
>
> --
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
>    Python as a HDL: http://www.myhdl.org
>    VHDL development, the modern way: http://www.sigasi.com
>    Analog design automation: http://www.mephisto-da.com
>    World-class digital design: http://www.easics.com
>
>
> ------------------------------------------------------------------------------
> The Planet: dedicated and managed hosting, cloud storage, colocation
> Stay online with enterprise data centers and the best network in the
> business
> Choose flexible plans and management services without long-term contracts
> Personal 24x7 support from experience hosting pros just a phone call away.
> http://p.sf.net/sfu/theplanet-com
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>

Re: [myhdl-list] verilog conversion issue (discrepancy between Python2.5 and 2.6)

[Jan D. <ja...@ja...>]

Could you show the error messages?

Both options seem to work for me.

Jan

Jose Ignacio Villar wrote:
> Hi all,
> some time ago i developed an lcd controller using Myhdl 0.6 and Python 
> 2.5 that can be found on opencores 
> (http://www.opencores.org/project,wb_lcd).
> 
> This week I updated my system to Python 2.6 and bleeding edge branch of 
> Myhdl. But when I tried to convert it to Verilog it started shouting 
> because of some lines that were already working with Python 2.5.
> 
> The problem is about the following kind of generators:
> 
>     @always_comb
>     def output_tx_or_init_select():
>         testOut.next = (state == t_State.SEARCH) | (state == 
> t_State.CONFIRM)
>        
> that in Python 2.6 used to generate the following verilog code:
> 
> assign testOut = ((state == 3'b001) | (state == 3'b010));
> 
> Everything fixed up by changing "|" operator by an Python "or":
> 
>     @always_comb
>     def output_tx_or_init_select():
>         testOut.next = (state == t_State.SEARCH) or (state == 
> t_State.CONFIRM)
> 
> and now it generates:
> 
> assign testOut = ((state == 3'b001) || (state == 3'b010));
> 
> Although both are working in my fpga, and from the verilog point of view 
> (If I'm not mistaken) are functionally equivalent, should Python 2.6 be 
> able to extract correct code for the first approach?
> I'd like to hear what experts think about it before spending several 
> days digging in the code to find taht I was wrong.
> 
> Kind Regards,
> Jose Ignacio Villar.
> 
> José Ignacio Villar <jo...@dt... <mailto:jo...@dt...>>
> Departamento de Tecnología Electrónica
> Escuela Técnica Superior de Ingeniería Informática
> Universidad de Sevilla
> Avda. Reina Mercedes, s/n
> 41012 - Sevilla (Spain)
> 
> Tlf: 954 55 99 62
> Fax: 954 55 27 64
> 
> 
> ------------------------------------------------------------------------
> 
> ------------------------------------------------------------------------------
> The Planet: dedicated and managed hosting, cloud storage, colocation
> Stay online with enterprise data centers and the best network in the business
> Choose flexible plans and management services without long-term contracts
> Personal 24x7 support from experience hosting pros just a phone call away.
> http://p.sf.net/sfu/theplanet-com
> 
> 
> ------------------------------------------------------------------------
> 
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

[myhdl-list] verilog conversion issue (discrepancy between Python2.5 and 2.6)

[Jose I. V. <jv...@gm...>]

Hi all,
some time ago i developed an lcd controller using Myhdl 0.6 and Python 2.5
that can be found on opencores (http://www.opencores.org/project,wb_lcd).

This week I updated my system to Python 2.6 and bleeding edge branch of
Myhdl. But when I tried to convert it to Verilog it started shouting because
of some lines that were already working with Python 2.5.

The problem is about the following kind of generators:

    @always_comb
    def output_tx_or_init_select():
        testOut.next = (state == t_State.SEARCH) | (state ==
t_State.CONFIRM)

that in Python 2.6 used to generate the following verilog code:

assign testOut = ((state == 3'b001) | (state == 3'b010));

Everything fixed up by changing "|" operator by an Python "or":

    @always_comb
    def output_tx_or_init_select():
        testOut.next = (state == t_State.SEARCH) or (state ==
t_State.CONFIRM)

and now it generates:

assign testOut = ((state == 3'b001) || (state == 3'b010));

Although both are working in my fpga, and from the verilog point of view (If
I'm not mistaken) are functionally equivalent, should Python 2.6 be able to
extract correct code for the first approach?
I'd like to hear what experts think about it before spending several days
digging in the code to find taht I was wrong.

Kind Regards,
Jose Ignacio Villar.

José Ignacio Villar <jo...@dt...>
Departamento de Tecnología Electrónica
Escuela Técnica Superior de Ingeniería Informática
Universidad de Sevilla
Avda. Reina Mercedes, s/n
41012 - Sevilla (Spain)

Tlf: 954 55 99 62
Fax: 954 55 27 64

Re: [myhdl-list] VHDL Cosimulation with GHDL

[Jan D. <ja...@ja...>]

Christopher Felton wrote:
> I created a quick page to capture some of the investigations for 
> Cosimulation with GHDL, http://www.myhdl.org/doku.php/dev:vhdl_cosim.
> 
> I noticed in previous newsgroup threads this was discussed some and it 
> was mentioned, back then, to start a wiki page to capture some of the 
> details.  If anyone has information to contribute please feel free to 
> update the page.

Thanks for starting this, I have also added the page to the
sidebar (dev:sidebar).

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

Re: [myhdl-list] Help with initial config of MyHDL on Ubuntu 9.04

[Jan D. <ja...@ja...>]

Kevin Stanton wrote:
> Chris,
> 
> Thanks for your help.  I actually had to do:
> 
> hg clone http:/hg.myhdl.org/myhdl <http://hg.myhdl.org/myhdl> myhdl
> 
> But once I did that, I did:
> 
> sudo python setup.py install
> 
> And then ran the rs232.  Everything works!

Yes, there was an issue related to the more general use
of decorators, fixed in development.

> Should probably cut a new release...

You have a point :-)

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

[myhdl-list] VHDL Cosimulation with GHDL

[Christopher F. <chr...@gm...>]

I created a quick page to capture some of the investigations for
Cosimulation with GHDL, http://www.myhdl.org/doku.php/dev:vhdl_cosim.

I noticed in previous newsgroup threads this was discussed some and it was
mentioned, back then, to start a wiki page to capture some of the details.
 If anyone has information to contribute please feel free to update the
page.

.chris

Re: [myhdl-list] Help with initial config of MyHDL on Ubuntu 9.04

[Kevin S. <sta...@gm...>]

Chris,

Thanks for your help.  I actually had to do:

hg clone http:/hg.myhdl.org/myhdl myhdl

But once I did that, I did:

sudo python setup.py install

And then ran the rs232.  Everything works!

Should probably cut a new release...

Thanks again!

Kevin

On Sat, Jan 30, 2010 at 4:51 PM, Christopher Felton
<chr...@gm...>wrote:

> On 1/30/10 3:34 PM, Kevin Stanton wrote:
> > Hi,
> >
> > I can't seem to find anything on what might be going wrong, but I just
> > installed MyHDL and tried to run a few of the examples.
> >
> > I went into :
> >
> > cd myhdl-0.6/example/rs232
> >
> > and ran:
> >
> > python test_rs232.py
> >
> > All of the tests fail, and I get back several errors that look exactly
> > like this:
> >
> > Traceback (most recent call last):
> >    File "test_rs232.py", line 102, in testCharacterize
> >      Simulation(self.bench(tx_baud_rate)).run(quiet=1)
> >    File "/usr/local/lib/python2.6/dist-packages/myhdl/_Simulation.py",
> > line 132, in run
> >      waiter.next(waiters, actives, exc)
> >    File "/usr/local/lib/python2.6/dist-packages/myhdl/_Waiter.py", line
> > 113, in next
> >      (repr(clause), type(clause)))
> > TypeError: yield clause <myhdl._instance._Instantiator object at
> > 0xa1a506c> has type <class 'myhdl._instance._Instantiator'>
> >
> > I am not a novice at VHDL, or Python for that matter, but this error
> > message is confusing because it appears to be complaining about a
> > TypeError, but the types listed match...
> >
> > What am I missing?
>
> Which version of Python do you have?  I double checked the rs232 in the
> latest dev snapshot with python 2.6 with success.
>
> You can get the latest development snapshot from
>   http://www.myhdl.org/doku.php/dev:repo
> using mercurial.
>
> p.s. I also downloaded 0.6 and reproduced the same error, I am not sure
> what the error is but it does not fail with the latest development
> snapshot.
>
> Maybe a new release should be cut?  Probably would just be a bug fix
> release no new major features?
>
> Hope that helps.
> Chris Felton
>
>
>
> ------------------------------------------------------------------------------
> The Planet: dedicated and managed hosting, cloud storage, colocation
> Stay online with enterprise data centers and the best network in the
> business
> Choose flexible plans and management services without long-term contracts
> Personal 24x7 support from experience hosting pros just a phone call away.
> http://p.sf.net/sfu/theplanet-com
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>



-- 
Kevin R. Stanton
c | 734•846•3915
e | sta...@gm...

Re: [myhdl-list] Help with initial config of MyHDL on Ubuntu 9.04

[Christopher F. <chr...@gm...>]

On 1/30/10 3:34 PM, Kevin Stanton wrote:
> Hi,
>
> I can't seem to find anything on what might be going wrong, but I just
> installed MyHDL and tried to run a few of the examples.
>
> I went into :
>
> cd myhdl-0.6/example/rs232
>
> and ran:
>
> python test_rs232.py
>
> All of the tests fail, and I get back several errors that look exactly
> like this:
>
> Traceback (most recent call last):
>    File "test_rs232.py", line 102, in testCharacterize
>      Simulation(self.bench(tx_baud_rate)).run(quiet=1)
>    File "/usr/local/lib/python2.6/dist-packages/myhdl/_Simulation.py",
> line 132, in run
>      waiter.next(waiters, actives, exc)
>    File "/usr/local/lib/python2.6/dist-packages/myhdl/_Waiter.py", line
> 113, in next
>      (repr(clause), type(clause)))
> TypeError: yield clause <myhdl._instance._Instantiator object at
> 0xa1a506c> has type <class 'myhdl._instance._Instantiator'>
>
> I am not a novice at VHDL, or Python for that matter, but this error
> message is confusing because it appears to be complaining about a
> TypeError, but the types listed match...
>
> What am I missing?

Which version of Python do you have?  I double checked the rs232 in the 
latest dev snapshot with python 2.6 with success.

You can get the latest development snapshot from
   http://www.myhdl.org/doku.php/dev:repo
using mercurial.

p.s. I also downloaded 0.6 and reproduced the same error, I am not sure 
what the error is but it does not fail with the latest development snapshot.

Maybe a new release should be cut?  Probably would just be a bug fix 
release no new major features?

Hope that helps.
Chris Felton