Re: [myhdl-list] Newbie questions

[Christopher F. <chr...@gm...>]

On Wed, Sep 14, 2016 at 4:39 PM, Mark Haun <ma...@ha...> wrote:

> Hi everyone,
>
> This is my first post to the list.  I'm new to MyHDL, using it with a
> Digilent "Arty" board and Vivado to learn FPGAs and HDL in general.  So
> far,
> I've found the documentation to be excellent and I haven't had any problems
> with simple LED flashing, PWM, etc.  Along the way I've accumulated some
> questions however:
>

Welcome,

A quick note, for the most part we have moved
conversations to discourse.myhdl.org, you might
get more responses there.


>
> 1) I would like to parameterize certain hardware modules like I see in the
> examples, e.g. I have the following "Timepulse" module:
>
> def Timepulse(reset, clk, q, interval=int(100e6)):
>     """ Generate a pulse for one clock cycle every <interval> clock cycles
>
>     q       timepulse output, with period equal to one clock
>     """
>     count = Signal(intbv(0, min=0, max=interval))
>
> Here "interval" is intended to be taken as a constant, for the purposes of
> simulation and conversion.  However, the Python code
>
>         if count == interval - 1:
>             count.next = 0
>         else:
>             count.next = count + 1
>
>         if count == interval - 1:
>             q.next = 1
>         elif count == 0:
>             q.next = 0
>
> is converted to the following Verilog:
>
>         if (($signed({1'b0, count}) == (100000000 - 1))) begin
>             count <= 0;
>         end
>         else begin
>             count <= (count + 1);
>         end
>         case (count)
>             (-'h1): begin
>                 q <= 1;
>             end
>             'h0: begin
>                 q <= 0;
>             end
>         endcase
>
> I don't understand where all the signed-arithmetic handling comes from.
> Intuitively, I thought the Verilog should be the same whether my expression
> uses "interval-1" or "interval", because both are large positive constants
> within the range of the count intbv.  But in fact when I take away the -1,
> the signed-number handling goes away too.  What am I missing?
>
> Something looks odd, someone will need to,
investigate a work around in the near term
is to use a separate variable

    countmax = interval-1
    # ...
    @always
        ...
        if count == countmax



> 2) When converting to Verilog, do the input/output port names always follow
> the names in the definition of the top-level Python function?  E.g. in the
> StopWatch tutorial, we have
>
> def StopWatch(tens_led, ones_led, tenths_led, startstop, reset, clock):
>
> so upon conversion, the Verilog code uses the names "tens_led", "ones_led",
> etc. as the inputs and outputs.  But when targeting a dev board, I would
> like to assign those ports to existing port names defined in my constraints
> file.
>
> It seems like there should be a way to give these names when I instantiate
> StopWatch, instead of having to make the names match between my Python code
> (at a high and logical level) and my constraints file (at a low and
> hardware
> level).  Am I missing some alternative?
>

The converted top-level block names will be the
port names in the converted verilog module.

Regards,
Chris


>
>