Re: [myhdl-list] Howto model a 16MHz clock?
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From: Christopher F. <chr...@gm...> - 2016-05-04 10:06:30
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Cristian, The MyHDL simulator is a discrete simulator, each time-step can only be an integer. This time-step is arbitrary it can map to any absolute unit or none. The MyHDL doesn't force a time-unit on the simulation. Absolute time doesn't mean much is the simulator, if your design only has one clock you can use what every integer number of simulation time-ticks for your clock. Example, I could simply say my 16MHz clock is 8 simulation time-steps: @always(delay(4)) def clock_generation(): clock.next = not clock If I do this, each simulation step will be 1/16e6/8 which is 7.8125ns. Personally, I would simply make my "16MHz" clock in simulation 16.1290323MHz (62 ns period) and keep the 1 sim step == 1 ns mapping. Regards, Chris On Wed, May 4, 2016 at 4:30 AM, Cristian Ramos <ram...@gm...> wrote: > Hi, > > The delay constructor only accepts integers: > > File "~/lib/python/myhdl-0.9.0-py2.7.egg/myhdl/_delay.py", line 39, in > __init__ raise TypeError(_errmsg) TypeError: arg of delay constructor > should be a natural integeer > > Also the Simulator object doesn't seem to accept a time resolution, like > in Verilog, where you have a "timescale 1ns/100ps". > > So for a simple clock generator: > > def DRIVE_CLK(): > while True: > yield delay(LOW) > CLK_OUT.next = 1 > yield delay(HIGH) > CLK_OUT.next = 0 > > > Where LOW and HIGH must be integers (ns), doesn't allow me to create an > arbitrary clock frequency (like in 16MHz). > > Any ideas are very welcome! > > Thanks, > > Regards > Cristian > > ------------------------------------------------------------------------------ > Find and fix application performance issues faster with Applications > Manager > Applications Manager provides deep performance insights into multiple > tiers of > your business applications. It resolves application problems quickly and > reduces your MTTR. Get your free trial! > https://ad.doubleclick.net/ddm/clk/302982198;130105516;z > _______________________________________________ > myhdl-list mailing list > myh...@li... > https://lists.sourceforge.net/lists/listinfo/myhdl-list > > |