[myhdl-list] Howto model a 16MHz clock?

[Cristian R. <ram...@gm...>]

Hi,

The delay constructor only accepts integers:

File "~/lib/python/myhdl-0.9.0-py2.7.egg/myhdl/_delay.py", line 39, in
__init__ raise TypeError(_errmsg) TypeError: arg of delay constructor
should be a natural integeer

Also the Simulator object doesn't seem to accept a time resolution, like in
Verilog, where you have a "timescale 1ns/100ps".

So for a simple clock generator:

def DRIVE_CLK():
while True:
yield delay(LOW)
CLK_OUT.next = 1
yield delay(HIGH)
CLK_OUT.next = 0


Where LOW and HIGH must be integers (ns), doesn't allow me to create an
arbitrary clock frequency (like in 16MHz).

Any ideas are very welcome!

Thanks,

Regards
Cristian