[myhdl-list] myhdl & co-simulation

[Edward V. <dev...@sb...>]

Hello All,

I have a Verilog file tb/wbdeppsimple.v which I hope to convert to myhdl.

I created the file tb/tb_wbdeppsimple.v to interface with myhdl.

I am creating the dr_wbdepp.py which creates "dr_wbdepp.v" with the command
dr_wbdepp.py --convert.

Should dr_wbdepp.v be included in the co-simulation or just a myhdl instance?

When I test the iverilog command from the command line, it does not get any errors.
iverilog -o ifdeppsimple tb/wbdeppsimple.v tb/tb_wbdeppsimple.v dr_wbdepp.v

The above command is called from dr_wbdepp.py --cosimtrace with the line below
cmd = "iverilog -o ifdeppsimple tb/wbdeppsimple.v tb/tb_wbdeppsimple.v dr_wbdepp.v"
which creates  tb/vcd/wbdeppsimple1.vcd.  

I then can use gtkwave to view the signals.

Should I create both a myhdl instance and instance in file tb_wbdeppsimple.v?

In the dr_wbdepp.py the tbstim instance, I am driving the signal o_para which drives
the signals o_b0 to o_b7.   

The file I am using are at https://github.com/develone/jpeg-2000-test/tree/master/xula2_fpga/parallel.

Any and all help is appreciated. Edward Vidal Jr. e-mail dev...@sb... 915-595-1613