Re: [myhdl-list] Inconsistency between simulation and conversion

[Nicolas P. <nic...@aa...>]

Le 28/04/2016 à 18:45, Christopher Felton a écrit :
>
>
> On Thu, Apr 28, 2016 at 8:05 AM, Nicolas Pinault <nic...@aa... 
> <mailto:nic...@aa...>> wrote:
>
>     Le 28/04/2016 à 13:47, Henry Gomersall a écrit :
>>     On 28/04/16 07:54, Nicolas Pinault wrote:
>>>     When using this statement "counter.next += 1" I get an error when
>>>     converting my design to VHDL :
>>>
>>>     myhdl.ConversionError: in file
>>>     Z:\myHDL_Tests\NoiseFilter\src\noise_filter.py, line 51:
>>>          Not supported: Augmented signal assignment
>>>
>>>     This makes sense.
>>>     However, this same statement does not trig any error when simulating the
>>>     design.
>>>     Is this the intended behaviour ?
>>>
>>     Incrementing .next is a slightly odd thing to want to do, but is
>>     possible given .next is likely an int type. Clearly it doesn't really
>>     make sense from the perspective of conversion.
>     To be consistent, I expect simulation to raise an exception as
>     conversion does.
>
>
> Hmmm, might require some conversation.  Nothing would
> prevent someone from incrementing (augmenting) next in
> modeling or verification - kinda odd but not sure if it should
> throw and error.
Well, at least, a warning should be generated when simulating.
I used augmented assignment inadvertently in a module. I made all the 
development with it without any problem. Then I got an error when 
converting. At first, this was a big surprise. I quickly found (and 
understood) the source of the problem but I would have preferred to be 
aware of the problem during simulation.
At first, I don't see any useful case of augmenting next attribute, even 
in simulation.

Nicolas
>
> Regards,
> Chris
>
>
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*Nicolas PINAULT
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*** ni...@aa... <mailto:ni...@aa...>

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