Re: [myhdl-list] Inconsistency between simulation and conversion

[Christopher F. <chr...@gm...>]

On Thu, Apr 28, 2016 at 8:05 AM, Nicolas Pinault <nic...@aa...> wrote:

> Le 28/04/2016 à 13:47, Henry Gomersall a écrit :
>
> On 28/04/16 07:54, Nicolas Pinault wrote:
>
> When using this statement "counter.next += 1" I get an error when
> converting my design to VHDL :
>
> myhdl.ConversionError: in file
> Z:\myHDL_Tests\NoiseFilter\src\noise_filter.py, line 51:
>     Not supported: Augmented signal assignment
>
> This makes sense.
> However, this same statement does not trig any error when simulating the
> design.
> Is this the intended behaviour ?
>
>
> Incrementing .next is a slightly odd thing to want to do, but is
> possible given .next is likely an int type. Clearly it doesn't really
> make sense from the perspective of conversion.
>
> To be consistent, I expect simulation to raise an exception as conversion
> does.
>
>
Hmmm, might require some conversation.  Nothing would
prevent someone from incrementing (augmenting) next in
modeling or verification - kinda odd but not sure if it should
throw and error.

Regards,
Chris