Re: [myhdl-list] Inconsistency between simulation and conversion

[Samuele D. <sm...@gm...>]

On Thu, Apr 28, 2016 at 1:47 PM, Henry Gomersall <he...@ma...> wrote:

> On 28/04/16 07:54, Nicolas Pinault wrote:
> > When using this statement "counter.next += 1" I get an error when
> > converting my design to VHDL :
> >
> > myhdl.ConversionError: in file
> > Z:\myHDL_Tests\NoiseFilter\src\noise_filter.py, line 51:
> >     Not supported: Augmented signal assignment
> >
> > This makes sense.
> > However, this same statement does not trig any error when simulating the
> > design.
> > Is this the intended behaviour ?
> >
>
> Incrementing .next is a slightly odd thing to want to do,


I would remove slightly to the sentence :).
You are supposed to do "counter.next = counter+1" and not "counter.next =
counter.next+1"

Simulation in MyHDL is just execution of your code and you are allowed to
do nasty things!

Samuele