Re: [myhdl-list] Inconsistency between simulation and conversion

[Henry G. <he...@ma...>]

On 28/04/16 07:54, Nicolas Pinault wrote:
> When using this statement "counter.next += 1" I get an error when
> converting my design to VHDL :
> 
> myhdl.ConversionError: in file
> Z:\myHDL_Tests\NoiseFilter\src\noise_filter.py, line 51:
>     Not supported: Augmented signal assignment
> 
> This makes sense.
> However, this same statement does not trig any error when simulating the
> design.
> Is this the intended behaviour ?
> 

Incrementing .next is a slightly odd thing to want to do, but is
possible given .next is likely an int type. Clearly it doesn't really
make sense from the perspective of conversion.

Henry