[myhdl-list] Inconsistency between simulation and conversion

[Nicolas P. <nic...@aa...>]

Hi,

When using this statement "counter.next += 1" I get an error when 
converting my design to VHDL :

myhdl.ConversionError: in file 
Z:\myHDL_Tests\NoiseFilter\src\noise_filter.py, line 51:
     Not supported: Augmented signal assignment

This makes sense.
However, this same statement does not trig any error when simulating the 
design.
Is this the intended behaviour ?

Nicolas


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*Nicolas PINAULT
R&D electronics engineer
*** ni...@aa... <mailto:ni...@aa...>

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