Re: [myhdl-list] Dual port ram, mixed width byte enables.

[Josy B. <jos...@gm...>]

Christopher Felton <chris.felton <at> gmail.com> writes:

> 
> 
> 
> On Tue, Apr 19, 2016 at 7:32 AM, Samuele Disegna <smldis <at> 
gmail.com> wrote:Yes! There is a multidimensional array that enables 
indexing of the smaller port (or the ability to have byte enables).
> 
> Yes that will be a problem :( 
> 
> There are a couple options: first, try and rework the example without 
the multidimension array.  Second, you could use the user defined code 
and wrap the template.  That would probably be the fastest and you would 
be able to still model the same logic in myhdl just not convert the 
multidim array.
> 

Chris, Samuele,

It needs to be a proper multidim VHDL array to have Quartus infer an 
'altsyncram'. You can try using one single-dimension array per byte-
enable, but then you will end up with multiple 'altsyncram'.
So there is only the second option left; write a model in MyHDL for the 
testbench and include 'user defined code' for conversion.
It will be possible using the future/proposed 'myhdl.Array' type.(I have 
that working in my local branch, but with the new '@block' decorator 
making a proper PR is a lot more work. And I have indulged in a few more 
'enhancements'. Maybe I should start sharing those first)

Regards,

Josy