Re: [myhdl-list] Dual port ram, mixed width byte enables.

[Samuele D. <sm...@gm...>]

Yes! There is a multidimensional array that enables indexing of the smaller
port (or the ability to have byte enables).

This is my rough code for symmetric ports:

from myhdl import *

class ram_port():
    def __init__(self,WIDTH,DEPTH):
        self.addr = Signal(intbv(0,min=0,max=DEPTH))
        self.we = Signal(False)
        self.din = Signal(intbv(0)[WIDTH:])
        self.dout = Signal(intbv(0)[WIDTH:])

@block
def ram_dual_port(clk,ram_port1,ram_port2,WIDTH,DEPTH):
    mem = [Signal(intbv(0)[WIDTH:]) for i in range(DEPTH)]

    @always(clk.posedge)
    def wr_port1():
        ram_port1.dout.next = mem[ram_port1.addr]
        if ram_port1.we:
            mem[ram_port1.addr].next = ram_port1.din

    @always(clk.posedge)
    def wr_port2():
        ram_port2.dout.next = mem[ram_port2.addr]
        if ram_port2.we:
            mem[ram_port2.addr].next = ram_port2.din
    return instances()

WIDTH = 8
DEPTH = 1000
clk = Signal(False)
p1 = ram_port(WIDTH,DEPTH)
p2 = ram_port(WIDTH,DEPTH)
ram = ram_dual_port(clk,p1,p2,WIDTH,DEPTH)

ram.convert(hdl='VHDL')



On Tue, Apr 19, 2016 at 12:39 PM, Christopher Felton <chr...@gm...
> wrote:

> On 4/18/16 12:56 PM, Samuele Disegna wrote:
> > Hi MyHDLs, Is there a way to implement a dual port ram with mixed
> > width ports and or byte enables?
> >
> > The template to infer one with Altera tools is something like this in
> > VHDL:
>
> You should be able to duplicate the template in
> MyHDL.  Is there a concern or specific issue you
> are having trouble with?
>
> Regards,
> Chris
>
>
>
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