Re: [myhdl-list] Dual port ram, mixed width byte enables.

[Christopher F. <chr...@gm...>]

On 4/18/16 12:56 PM, Samuele Disegna wrote:
> Hi MyHDLs, Is there a way to implement a dual port ram with mixed
> width ports and or byte enables?
>
> The template to infer one with Altera tools is something like this in
> VHDL:

You should be able to duplicate the template in
MyHDL.  Is there a concern or specific issue you
are having trouble with?

Regards,
Chris