Re: [myhdl-list] verilog to MyHDL conversion
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Re: [myhdl-list] verilog to MyHDL conversion
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From: David B. <dav...@ya...> - 2016-03-22 02:07:17
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I was wondering if MyHDL / Python supports functional oriented programming and development for FPGAs ??
Thanks,
David Blubaugh
On Monday, March 21, 2016 8:36 PM, Edward Vidal <dev...@sb...> wrote:
Chris,I used a module top_level which uses a dd dummy method to include the verilog code using a
dd.verilog_code = \ statement.
python jtagser.py --convert.
see https://gist.github.com/609d03b3296dd3610343.git
This now includes BSCAN_SPARTAN6 like the file jtagser.v
Thanks,
Edward Vidal Jr. e-mail dev...@sb... 915-595-1613
On Sunday, March 20, 2016 5:09 PM, Edward Vidal <dev...@sb...> wrote:
Chris,The following o_rx_data.next = { ck_tdi, o_rx_data[7:1] } converts to
o_rx_data <= ck_tdio_rx_data[7-1:1]; should be o_rx_data <= { ck_tdi, o_rx_data[7:1] };
What is this statement doing?
Still must be missing something? Not getting anything in the .v file created.Is this what you wanted me to do?
capture = Signal(bool(0))
drck = Signal(bool(0))
reset = Signal(bool(0))
RUNTEST = Signal(bool(0))
SEL = Signal(bool(0))
SHIFT = Signal(bool(0))
TCK = Signal(bool(0))
TDI = Signal(bool(0))
TMS = Signal(bool(0))
UPDATE = Signal(bool(0))
TDO = Signal(bool(0))
def bscan_spartan6(capture,drck,reset,RUNTEST,SEL,SHIFT,TCK,TDI,TMS,UPDATE,TDO):
'''
mark the outputs with sig.driven = True
maybe put some logic to stub out minimal behavior
'''
capture.driven = True
drck.driven = True
reset.driven = True
RUNTEST.driven = True
SEL.driven = True
SHIFT.driven = True
TCK.driven = True
TDI.driven = True
TMS.driven = True
UPDATE.driven = True
TDO.driven = True
Thanks,
Edward Vidal Jr. e-mail dev...@sb... 915-595-1613
On Sunday, March 20, 2016 12:11 PM, Christopher Felton <chr...@gm...> wrote:
On 3/20/16 10:59 AM, Edward Vidal wrote:
> See the verilog file and my attempt to convert at
> https://gist.github.com/95d06caf184fc1976d65.git
> Are verilog && in myhdl written as & this? I was getting
You would use "and" in Python/MyHDL.
> The code that starts with BSCAN_SPARTAN6, I believe came
> from a template. I was hoping on user jtag.verilog_code = \
> to include it, in my the generated verilog file. When I move
> line 72 """ to line 74 of jtagser.py I get the quoted text but not
> the other instance that I am trying to convert.
For this you want to create a separate block (module)
and override the contents of the block:
def bscan_spartan6(capture, drck, reset, ...)
# mark the outputs with sig.driven = True
# maybe put some logic to stub out minimal behavior
bscan_spartan6.verilog_code = \
"""
BSCAN_SPARTN6
#(.JTAG_CHAIN(1)))
BSCANE2_inst(
.CAPTURE($capture),
.DRCK($drck),
...
Hope that helps,
Chris
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