Re: [myhdl-list] verilog to MyHDL conversion

[Christopher F. <chr...@gm...>]

On 3/20/16 10:59 AM, Edward Vidal wrote:
> See the verilog file and my attempt to convert at
> https://gist.github.com/95d06caf184fc1976d65.git
> Are verilog && in myhdl written as & this?  I was getting

You would use "and" in Python/MyHDL.


> The code that starts with BSCAN_SPARTAN6, I believe came
> from a template.  I was hoping on user jtag.verilog_code = \
> to include it, in my the generated verilog file.  When I move
> line 72 """ to line 74 of jtagser.py I get the quoted text but not
> the other instance that I am trying to convert.

For this you want to create a separate block (module)
and override the contents of the block:

     def bscan_spartan6(capture, drck, reset, ...)
         # mark the outputs with sig.driven = True
         # maybe put some logic to stub out minimal behavior

    bscan_spartan6.verilog_code = \
    """
    BSCAN_SPARTN6
        #(.JTAG_CHAIN(1)))
    BSCANE2_inst(
        .CAPTURE($capture),
        .DRCK($drck),
        ...


Hope that helps,
Chris