[myhdl-list] [GSoc 16] Regarding JPEG Encoder

[Vikram P. <vik...@st...>]

Hi,
I would love to work on JPEG Encoder as a part of GSoC. 

I have previous experience of Verilog, VHDL. I have synthesised 2D-DCT 
module (an implementation of Chenn's Algorithm), Quantiser and FIFO 
working modules along with their test bench in Verilog.I have a decent 
experience with python and have a good experience with designing VLSI 
architectures and Digital circuits.

I would love to know more about the project and how to get started.

Thanks,
Vikram
Electronics and Communication Engineering
IIIT Hyderabad