Re: [myhdl-list] GSoC'16 | JPEG Encoder

[Henry G. <he...@ma...>]

On 02/03/16 13:59, Henry Gomersall wrote:
> E.g. when the DSP has to be pipelined to maximize throughput, it's no
> longer just a multiplier and the code has to reflect that. You could
> create a multiplier block with pipeline stages incorporated, but then
> you're more or less doing as I suggest (and still with no guarantees the
> synthesizer will do the right thing).

I wrote an inline complex multiplier based around a single DSP which
really gets into the guts of the DSP core. It's hard to see how one
would do this in plain VHDL with a hope that it would be inferred
correctly (the difficulty is in things like flicking control registers
mid pipeline from multiply-add to multiply-accumulate to
multiply-deccumulate).

Cheers,

Henry