Re: [myhdl-list] GSoC'16 | JPEG Encoder

[Henry G. <he...@ma...>]

On 02/03/16 13:53, Christopher Felton wrote:
>> >
>> > Specifically, most FPGAs have various mutually incompatible primitives,
>> > things like DSPs and RAM blocks. It would be great, for example, to have
>> > a MyHDL DSP structure that can be _just used_, and then switched to
>> > support whatever hardware.
> "can be just used" on whatever hardware is best supported
> (most portable) when you have generic HDL without specific
> primitives.  You can guide the HDL so the synthesizer
> infers the correct primitives e.g. DSP blocks can safely
> be inferred when the correct widths, delay slots, etc.
> This could be controlled with a couple parameters and the
> HDL could be modular to fit various structures - maybe?
> 

Yeah, absolutely. The problem comes when really pushing the bounds.

E.g. when the DSP has to be pipelined to maximize throughput, it's no
longer just a multiplier and the code has to reflect that. You could
create a multiplier block with pipeline stages incorporated, but then
you're more or less doing as I suggest (and still with no guarantees the
synthesizer will do the right thing).

It was a broader point than GSoC - more me thinking out loud.

Cheers,

Henry