Re: [myhdl-list] GSoC'16 | JPEG Encoder

[Christopher F. <chr...@gm...>]

On 3/2/2016 4:45 AM, Martin Strubel wrote:
> Hi,
>
>> After going through the projects list, I found the JPEG Encoder
>> interesting, mainly because I know a bit of Verilog and basic
>> scripting in Python.
<snip>
>
> This is quite ambitious, really. I've gone through the fun designing
> a JPEG encoder IP, you might want to focus on a small partition of
> the entire project, like an efficient way to pack the huffman encoded
> bit stream at high pixel clocks (~150 MHz for Full HD) in MyHDL.

The students will not be starting from scratch, they will be
using existing open-source encoders [1] to "port".  But this
will not be a simple port, they will be creating a design that
is more modular, scalable, and reusable than the existing
version.  As well as having a more exhaustive set of tests.

> Unfortunately, I'm a VHDL guy, so I've taken the other road. For
> sure, you'll need the full understanding of the JPEG encoding basics
> (this can cost you a few months), and it definitely helps, if you're
> firm with the cosimulation techniques of your simulator, unless
> you're using MyHDL completely. You might find some pointers or
> inspiration here: http://www.section5.ch/vkit The docs are slightly
> outdated though, most components are now MyHDL instead VHDL. It is
> kinda tricky, to get the arithmetics right with MyHDL, but when not
> touching the DCT, you'll save yourself some hassle :-)

Since the reference design exists, I don't imagine they will
need to know the specific details of the various algorithms,
but they will need to show that the MyHDL version is functionally
the same as the reference designs.

We also plan to have two students on the JPEGEnc project, the
JPEGEnc blocks will be divided between two students.

Thanks for the comments!  It is all good information and things
the students need to be aware of.  Now it looks like they will
have access to a third reference design :)


[1] https://github.com/cfelton/test_jpeg