Re: [myhdl-list] GSoC'16 | JPEG Encoder

[Martin S. <ha...@se...>]

Hi,

> After going through the projects list, I found the JPEG Encoder
> interesting, mainly because I know a bit of Verilog and basic scripting
> in Python. The description of the idea mentioned that familiarity with
> digital circuits - wanted to know to what extent,could someone give an
> example of the same. I am new to this, so could someone please help me
> getting started. Could someone tell me what specific pre-requisites do I
> need to have to get started with this project?
> 

This is quite ambitious, really. I've gone through the fun designing a
JPEG encoder IP, you might want to focus on a small partition of the
entire project, like an efficient way to pack the huffman encoded bit
stream at high pixel clocks (~150 MHz for Full HD) in MyHDL.
Unfortunately, I'm a VHDL guy, so I've taken the other road.
For sure, you'll need the full understanding of the JPEG encoding basics
(this can cost you a few months), and it definitely helps, if you're
firm with the cosimulation techniques of your simulator, unless you're
using MyHDL completely.
You might find some pointers or inspiration here:
http://www.section5.ch/vkit
The docs are slightly outdated though, most components are now MyHDL
instead VHDL. It is kinda tricky, to get the arithmetics right with
MyHDL, but when not touching the DCT, you'll save yourself some hassle :-)

Cheers,

- Strubi