Re: [myhdl-list] Thanks for MyHDL & PLL's

[Mr C C. <ch...@be...>]

yeah the icestorm tools are sweet, programming just the cram is a nice 
option and blisteringly fast :)

the combination of MyHDL and icestorm is nice...

mind I have noticed some oddities for example comparing list/tuple intbv 
elements with a intbv is still defeating me... I guess I'm still trying 
to get my head round the subtleties !

On 25/02/16 22:39, Jan Coombs wrote:
> On Thu, 25 Feb 2016 21:03:22 +0000
> Mr C Camacho <ch...@be...> wrote:
>
>> Don't suppose you've got a saner example of including a
>> verilog module within a MyHDL do you? it's either way less
>> complex than it looks or I'm missing something here!
> I have wrapped Lattice library components to make them simulate
> or export for synthesis.
>
> The smallest wrapper I have is for a Lattice XO2 internal osc
> - 47 lines.
>
> Have also an iCE40 SB_RAM256X16.py with initialization, which I
> have used.
>
> I also started wrapping everything from the iCE40 primitive
> library, thinking I might ignore the synthesis tool and do it all
> in MyHDL, but most of this is untested.
>
> Have you noticed that the icestorm tools can program an iCE40
> part in just 2s?
>
> Let me know if you'd like anything emailed.
>
> Jan Coombs.