Re: [myhdl-list] Thanks for MyHDL & PLL's

[Christopher F. <chr...@gm...>]

>
> One thing I can't seem to find any info about - what do I do with the
> icepll output
>
> here's a verilog example
> https://github.com/SubProto/icestick-vga-test/blob/master/vga.v
>
> how do I replicate the SB_PLL40_CORE and instance it in python (MyHDL)
>
> if that isn't possible, could someone give me an example wrapped in a
> custom verilog clause?

This isn't a minimilistic example or an iCE PLL example
but it is an example of wrapping a Xilinx MMCM
https://github.com/cfelton/rhea/blob/master/rhea/vendor/xilinx/_device_clock_mgmt.py

Regards,
Chris

>
> on the 8k board how do you instance both PLL's - do you have to do
> anything specific if you want to use both sources and also feed one into
> the other?

No you shouldn't have to do anything special, just
instance the two PLLs and connect as you want.

Regards,
Chris