[myhdl-list] Thanks for MyHDL & PLL's

[Mr C C. <ch...@be...>]

I'm genuinely pleasantly surprised by how much difference MyHDL make to 
the ease of use and general accessibility of FPGA's (you never know 
manufacturers might be so impressed they send you all their internal 
docs ;) - okay you can stop laughing now - but wouldn't they sell more 
chips? )

My previous experience has been with some 6GB monstrosity of a tool 
chain and well... it just wasn't fun, using MyHDL and Icestorm is a very 
much more pleasant and productive experience

Thanks!

One thing I can't seem to find any info about - what do I do with the 
icepll output

here's a verilog example
https://github.com/SubProto/icestick-vga-test/blob/master/vga.v

how do I replicate the SB_PLL40_CORE and instance it in python (MyHDL)

if that isn't possible, could someone give me an example wrapped in a 
custom verilog clause?

on the 8k board how do you instance both PLL's - do you have to do 
anything specific if you want to use both sources and also feed one into 
the other?

Once again thanks for MyHDL, fantastic work!

C