Re: [myhdl-list] A module that connects signals if names match
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From: Christopher F. <chr...@gm...> - 2016-02-25 17:11:49
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On 2/25/2016 11:00 AM, Ben Reynwar wrote: > That makes sense. So when I'm experimenting with things like this, > I can write a generic modules using interfaces, but when testing it, > wrap it with an explicit module so that I don't have any interfaces > in my top-level. Yes, that is a recipe for success :) I will do things like the following to make the explicit ports in the top-levels easier to manage def my_core_top( # somewhat painful explicitly listing the ports # ... ) portmap = dict(clock=Signal(bool(0)) portmap.update(axi4lite_portmap) my_core_top.portmap = portmap In my testbenches and conversion scripts I don't need to type out all those ports again portmap = my_core_top.portmap clock = portmap['clock'] axi = AXI4LiteInterface(portmap) tbdut = my_core_top(**portmap) To me this makes sense because a top-level maps to an explicit static hardware device, having tools to map the explicit portmap to the generic interfaces is a good approach, in my opinion. Regards, Chris |