Re: [myhdl-list] A module that connects signals if names match

[Christopher F. <chr...@gm...>]

On 2/25/2016 8:34 AM, Ben Reynwar wrote:
> Thanks for the help Chris.  I've updated the code so that I have 3 input
> signals (i_a, i_b, i_c) and 2 output signals (o_b, o_c).
>
> The name mangling converts both i_b and i_c to i, and both o_b and o_c to
> o.  How should I get around this issue?
>

This seems to be a bug, I did an explicit version [1]
and and got similar results:

     def top_level_assign(intf_in, intf_out):
         m1 = assign(intf_in.b, intf_out.b)
         m2 = assign(intf_in.c, intf_out.c)
         return  m1, m2

     module top_level_assign (
         b,
         b,
         a,
         a,
         intf_in_a
     );

There might be an issue created for this already, I
need to check (vaguely recall discussing something
similar in the past).  If not an issue should be
created.

Regards,
Chris

[1] https://gist.github.com/cfelton/81c680347dc6b2d5a458