Re: [myhdl-list] A module that connects signals if names match
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From: Ben R. <be...@re...> - 2016-02-25 04:00:40
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And five minutes after posting I found a bug in my code that explained why the simulation wasn't working. I had inputs and outputs wrong way round! However, I still am having issues with the verilog generation. On Wed, Feb 24, 2016 at 8:54 PM, Ben Reynwar <be...@re...> wrote: > Hi all, > > I'm experimenting with MyHDL and am trying to write a module that connects > inputs and outputs based on the signals names. I doing this to get a feel > for what MyHDL can and cannot do. > > The code is at https://gist.github.com/benreynwar/5963c2658883322be7c4 > including the generated verilog. > > The module "Reduces" takes a generic input interface, and a generic output > interface. All signals which have the same name in both the input and > output interface are connected. > Any other signals are ignored. > > It simulates without complaining but does not give the output I would > expect. The outputs remain unchanged. > > It generates verilog without error, but the generated verilog does not > match what I would expect. > > I expect I'm going about this wrong, since I have little experience with > MyHDL. Any pointers would be appreciated. > > Cheers, > Ben > |