Re: [myhdl-list] (rhea) icestick_blinky_host.py

[Christopher F. <chr...@gm...>]

On 2/5/16 3:02 PM, Edward Vidal wrote:
> Hi All,
>
>
> My concern was the setting the frequency to 50e6.  Is this just for
> the UART since it has a baud rate?

I am confused, why or how are you setting it
to 50e6?  Like I said before you should just
be using the clock passed during the build
so you shouldn't have to set it.

>
> In the xula2.ucf I do see NET "clock" TNM_NET = "clock"; TIMESPEC
> "TS_clock" = PERIOD "clock" 83.3333333 ns HIGH 50%; which is the
> 12MHz of the XulA2 board
 >
 > While on the catboard.pcf I never see anything related to timing.
 >

The clock constraints should be written out for
the ice flow (iceriver) as well.  I forget if
this is something that has not been implemented
yet or not supported in arachne.

In this case, correct the frequency is used for
for any time based things: buad, 1 second tick,
etc.

> Running python input_clk.py --convert generates cat_top.v. Running
> python input_clk.py --build generates iceriver/catboard.v
>
> In the catboard.v I see wire cmd_inst_clock; which is not in
> cat_top.v.
>
> Also many of the modules in catboard.v have this line always
> @(posedge cmd_inst_clock) begin

If you don't think it is correct you would have
to trace it out in the Verilog source.  Name
changes do occur in conversion.  If your simulation
tests pass it is probably ok and name changes
occurred in the conversion.

Regards,
Chris