Re: [myhdl-list] (rhea) icestick_blinky_host.py

[Christopher F. <chr...@gm...>]

On 2/5/2016 11:05 AM, Edward Vidal wrote:
> Hi All,I am trying to add these memmap_command_bridge,
> glbl_timer_ticks, Barebone and FIFOBus cores from (rhea)
> icestick_blinky_host.py  to my code. On the CAT-Board on pg 6 of the
> schematic the 100MHz oscillator provides
>
> signal USER_CLK which is connected to C8 of ICE40-HX8K-CT256.
>
> The catboard.pcf created with rhea, in the catboard.pcf file I see
> set_io clock C8.
>
> Do these 2 lines above have an impact on the ICE40 clock?
>
> clock=Clock(0, frequency=50e6) glbl = Global(clock, None)

Yes, they would but it would be an unexpected effect.  If
you are using the rhea.build, it will map the ports to
the board definitions - as long as the port names match
the pin names (which are typically the names from the
schematic / documents).

You can see in the CAT board definition this is already
defined: 
<https://github.com/cfelton/rhea/blob/master/rhea/build/boards/lattice/_catboard.py#L18>
This will be mapped to the `clock` port in your top-level
module.  So it should "just work" :)

The idea, if designing for a specific board you will have
a top-level for that board:

     def my_cat_design(clock, led, sw):
         # you might want to do more, like debounce,
         # sync, etc.
	reset = sw(0)  # sw[0] reset, get shadow signal
         glbl = Global(clock, reset)

Do note, when I tested the `memmap_command_bridge` on the
icestick it did not work with iceriver (yosys+aracne+icestorm)
but it did work with the icecube2.

Hope that helps,
Chris