Re: [myhdl-list] how is it with gtkwave and tracing interfaces?

[David B. <da...@be...>]

did you run it with interface modification?  the test bench I attached does 
not use interface and runs just fine. when you modify it as I have 
described in my last email, I.e calling register using self.rc instead of 
clock and reset,  gtkwave does not show me the interface signals.


On January 31, 2016 12:44:38 Marcel Hellwig 
<1he...@in...> wrote:

> Hmmm. When I open gtkwave and look at the i_dut instance, I can see 5
> signals: ClkxC, DxD[7:0], DxE, QxD[7:0], ResetxRn
>
> so.. i don't get your problem, sorry :/
>
> Greetings
> Marcel
>
> On 31.01.2016 11:42, David Belohrad wrote:
>> Dear All,
>>
>> based on my previous question on how to do efficiently testbench I have 
>> made a small demo register, including a testbench to see the signals in the 
>> gtkwave (see below). It is a combination of Marcel's and Christopher's 
>> approaches. In addition I have added an interface having reset and clock 
>> signals.
>>
>> The testbench how it is below works fine, and in GTKwave under i_dut I have 
>> all the signals, including a reset and clock, so ... satisfaction.
>>
>> How, I want to pass the interface into the DUT, hence line
>>
>> self.args = (self.rc.ClkxC, self.rc.ResetxRN, self.DxD, self.DxE, self.QxD)
>>
>> becomes
>>
>> self.args = (self.rc, self.DxD, self.DxE, self.QxD)
>>
>> and register declaration:
>>
>> def register(ClkxC, ResetxRN, DxD, DxE, QxD):
>>     @always_seq(ClkxC.posedge, ResetxRN)
>>
>> becomes
>>
>> def register(rc, DxD, DxE, QxD):
>>     @always_seq(rc.ClkxC.posedge, rc.ResetxRN)
>>
>>
>> and now the mystery comes. I can run such testbench, and it runs again 
>> fine. Problem is, when looking on gtkwave signals, the interface signals 
>> are not there. Hence I cannot see ClkxC and I cannot see ResetxRN. I can 
>> somehow see the clock, as i_dut instantiates ClockList with register 
>> ClockList(0), which indeed contains the clock. ResetxRN however disappeared.
>>
>> Why is that? And how can I avoid this?
>>
>> thanks
>>
>> .d.
>>
>>
>>
>> --------------------------------------------------------------------------------
>> # really disgusting way how to link relative
>> import sys
>> sys.path.append('/home/belohrad/git/didt/MyHDL/rhea')
>>
>> from myhdl import *
>> import unittest
>> from functools import wraps
>> from rhea.system.clock import *
>> from rhea.system.reset import *
>>
>> class RC(object):
>>     def __init__(self):
>>         self.ClkxC = Clock(0, frequency=160e6)
>>         self.ResetxRN = Reset(0, active = 0, async=True)
>>
>>
>> def register(ClkxC, ResetxRN, DxD, DxE, QxD):
>>     @always_seq(ClkxC.posedge, ResetxRN)
>>     def ilogic():
>>         if DxE:
>>             QxD.next = DxD
>>     return ilogic,
>>
>> _trace = False
>>
>> # decorator to trace problematic function
>> def trace(func):
>>     func.trace = True
>>     return func
>>
>> #decorator with main bench initialization
>> def myhdltest(func):
>>     @wraps(func)
>>     def wrapper(self):
>>
>>         def testbench():
>>             @instance
>>             def clockGen():
>>                 yield self.rc.ClkxC.gen()
>>
>>             @instance
>>             def reset():
>>                 yield self.rc.ResetxRN.pulse( (10,12,18) )
>>
>>             @instance
>>             def stimulus():
>>                 yield func(self)
>>                 raise StopSimulation
>>
>>             i_dut = self.dut(*self.args)
>>             return i_dut, stimulus, reset, clockGen
>>
>>         #tracedec = getattr(wrapper, 'trace', None)  # True or None
>>         #tracesel = getattr(self, 'trace', None)  # True or None
>>         #tracecmd = _trace  # True or False
>>         #trace = (x for x in (tracedec, tracesel, tracecmd) if x is not None).next()
>>
>>         g = traceSignals(testbench) #if trace else self.dut(*self.args)
>>         Simulation(g).run()
>>
>>     return wrapper
>>
>>
>> class testRegister(unittest.TestCase):
>>
>>     def setUp(self):
>>         # prepare instance of the item
>>
>>         self.DxD, self.QxD = [Signal(intbv(0)[8:]) for x in xrange(2)]
>>         self.DxE = Signal(bool(0))
>>         self.rc = RC()
>>
>>         # test instance
>>         self.args = (self.rc.ClkxC, self.rc.ResetxRN, self.DxD, self.DxE, self.QxD)
>>         self.dut=register
>>
>>
>>
>>     @trace
>>     @myhdltest
>>     def testRegister(self):
>>
>>         # stimulus
>>         self.rc.ClkxC.next = 0
>>         self.DxD.next = 0
>>         self.DxE.next = 1
>>         yield join(self.rc.ClkxC.posedge, self.rc.ResetxRN.posedge)
>>
>>         # reset stage finished
>>         self.DxD.next = 1
>>         for i in range(10):
>>             yield (self.rc.ClkxC.posedge)
>>             self.DxD.next = 0
>>         yield(delay(150))
>>
>>
>>
>> unittest.main()
>>
>> ------------------------------------------------------------------------------
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>
>
>
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