Re: [myhdl-list] Absolute timing

[Edward V. <dev...@sb...>]

Hi All,Yes Chris, what you provided helped quite a bit.
I have continued to add more work to the simulation and have tested on both the a 6 core AMD with Ubuntu 12.04 
and the RPi2B with RaspBian Jessie.
The results are below. 
 On a 6-Core AMD runningUbuntu 12.04 the simulation takes 
vidal@ws009:~/wkg/jpeg-2000-test/pc_fast_blinker_jpeg$time python test_top_a.py --testreal 1m6.287suser 1m6.036ssys 0m0.228s
On a RPi2B with pypy thesimulation takes 
time/opt/pypy-4.0.1-linux-armhf-raspbian/bin/pypy test_top_a.py --testreal 4m22.736suser 4m17.710ssys 0m2.180s
pi@mysshserver~/jpeg-2000-test/pc_fast_blinker_jpeg $ time python test_top_a.py--testreal 12m31.381suser 12m19.160ssys 0m2.330sUsing pypy provides a 1.43times improvement over python.
Simulation time in GTKWave.
23,039,990 ns 23.03 msec at50MHzIs this what I could expect on a XulA2-LX9 running at 120MHz or CAT-Board at 100MHz.

 
| 120000000 | 2.4 | 9.60E-003 |
| 100000000 | 2 | 1.15E-002 |


My simulation is "python test_top_a.py --test" https://github.com/develone/jpeg-2000-test/blob/master/pc_fast_blinker_jpeg/test_top_a.py

In the document https://github.com/develone/jpeg-2000-test/blob/master/pc_fast_blinker_jpeg/multi_instance_simulation.pdf 
In Appendix B I have python code that I need to convert to HDL, since it is currently used twice in the simulation.What is the best method to do this conversion?  Would like to use 16 instances instead of 4 which I am currently using.
 Thanks in advance.Regards,
Edward Vidal Jr. e-mail dev...@sb... 915-595-1613 

    On Wednesday, January 27, 2016 11:28 AM, Christopher Felton <chr...@gm...> wrote:
 

 On 1/27/2016 10:01 AM, Edward Vidal wrote:
> Hello All, When you convert to Verilog, I see that `timescale
> 1ns/10ps near the top of the file .I don't see any timing information
> when you convert to VHDL. On the CAT-Board the default clock is
> 100MHz & on XulA2-LX9 the default clock is 12MHz.With the DCM I
> convert to 120MHz. For my simulation my clock is always 20nsec or
> 50MHz.  Why? Can someone explain? @always(delay(10)) def clkgen():
> clock.next = not clock If my simulation takes 1m35.611s using pypy,
> but total simulation time is 9139190 ns. What is the FPGA time?

The MyHDL simulator does not specify an absolute physical
time unit for each simulation time-step.  It's yours to
determine (e.g. `delay(1)` can be 1ns if you like).

It gets a little more complicated when creating VCD files
and converting.  When "tracing" the VCD file and the V*
time literals need to know the units.  For tracing the
time unit embedded in the VCD file and is controlled by
the `traceSignals.timescale` attribute and the default
is "1ns".

    In [2]: traceSignals.timescale
    Out[2]: '1ns'

If you are using the defaults and in your waveform viewer
you see 9,139,160 ns your real-time will be 9.1ms and
your clock will be the 50MHz as viewed in the waveform
viewer.

If I change `traceSignals.timescale = '1ps' and nothing
else in my test code.  The clock will be 50GHz and the
simulated time will be 9.1us as observed in the waveform
viewer

Hope that helps,
Chris


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