[myhdl-list] please help with best way how to construct unittest testbench

[David B. <da...@be...>]

Dear all,

my question is simple: when using unittest/testcase, one can write more testbenches. I have wrote one, like the one below. As you can see, the 'testbench' is quite long, as one has to initialize all the signals, instantiate the DUT, provide reset and clock, and it does nothing (yet).

I want to add a second test-bench, but I'd like to re-use the fraction of instantiation and initialization of the DUT. This is quite a work (not for this design, but for more complex designs). So far I have seen only testbenches, which were implementing each test case as a separate test function, which contained each time copy of signal assignments and instantiation of DUT. Is there any way, how to write a second test bench, and re-use the instances and signal assignments aready done? In fact, it would be great if I could just instantiate it once, assign signals, and then in the test functions just by driving the signals and compare with expected *without re-starting the simulation*.

Any hint appreciated.

thaaanks

.d.




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from unittest import TestCase

class testFIFO(TestCase):

    def __init__(self):
        self.FIFO_DEPTH = 4
        self.width = 8

    def testbench(self):
        # prepare instance of the item
        print "Testbench"

        rc = RC()
        DxD, QxD = [Signal(intbv(0)[self.width:]) for x in xrange(2)]
        DxE, QValidxS = [Signal(bool(0)) for x in xrange(2)]

        # test instance
        dut=fifo(rc, DxD, DxE, QxD, QValidxS, self.FIFO_DEPTH)

        # clock generation
        @always(delay(10))
        def clockGen():
            rc.ClkxC.next = not rc.ClkxC

        @instance
        def reset():
            rc.ResetxRN.next = 0
            yield(delay(147))
            rc.ResetxRN.next = 1

        # stimulus
        @instance
        def stimulus():
            rc.ClkxC.next = 0
            DxD.next = 0
            # yield (rc.ResetxRN.posedge)
            # yield (rc.ClkxC.posedge)
            yield join(rc.ClkxC.posedge, rc.ResetxRN.posedge)

            # unit
            self.assertEqual(QValidxS, 0)
            # reset stage finished
            for i in xrange(10):
                DxD.next = i
                yield (rc.ClkxC.posedge)
            DxD.next = 0

            yield(delay(200))
            raise StopSimulation()

        return dut, stimulus, clockGen, reset,

    def testOutputFlow(self):
        tb = traceSignals(self.testbench)
        sim = Simulation(tb)
        sim.run()
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