[myhdl-list] Absolute timing

[Christopher F. <chr...@gm...>]

On 1/27/2016 10:01 AM, Edward Vidal wrote:
> Hello All, When you convert to Verilog, I see that `timescale
> 1ns/10ps near the top of the file .I don't see any timing information
> when you convert to VHDL. On the CAT-Board the default clock is
> 100MHz & on XulA2-LX9 the default clock is 12MHz.With the DCM I
> convert to 120MHz. For my simulation my clock is always 20nsec or
> 50MHz.  Why? Can someone explain? @always(delay(10)) def clkgen():
> clock.next = not clock If my simulation takes 1m35.611s using pypy,
> but total simulation time is 9139190 ns. What is the FPGA time?

The MyHDL simulator does not specify an absolute physical
time unit for each simulation time-step.  It's yours to
determine (e.g. `delay(1)` can be 1ns if you like).

It gets a little more complicated when creating VCD files
and converting.  When "tracing" the VCD file and the V*
time literals need to know the units.  For tracing the
time unit embedded in the VCD file and is controlled by
the `traceSignals.timescale` attribute and the default
is "1ns".

     In [2]: traceSignals.timescale
     Out[2]: '1ns'

If you are using the defaults and in your waveform viewer
you see 9,139,160 ns your real-time will be 9.1ms and
your clock will be the 50MHz as viewed in the waveform
viewer.

If I change `traceSignals.timescale = '1ps' and nothing
else in my test code.  The clock will be 50GHz and the
simulated time will be 9.1us as observed in the waveform
viewer

Hope that helps,
Chris