Re: [myhdl-list] simulation appears okay when programmed not getting all signals.
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Re: [myhdl-list] simulation appears okay when programmed not getting all signals.
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From: Jan C. <jen...@mu...> - 2016-01-23 08:35:55
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hi Edward, It was good to speak with you earlier this week. On Sat, 23 Jan 2016 01:18:28 +0000 (UTC) Edward Vidal <dev...@sb...> wrote: > Hello All, > ran python test_sending31.py --test which generates tb.vcd I cloned your git repo, installed rhea properly, changed to the relevant folder: /home/jan/.../EdwardVidal/git/jpeg-2000-test/pc_fast_blinker_jpeg then ran the above command: "pythontest_sending31.py" and found only these new files: ./ ├── [2016-01-23_07:40:11] iceriver │ ├── [2016-01-23_07:40:11] build_iceriver.log │ ├── [2016-01-23_07:40:11] catboard.bin │ ├── [2016-01-23_07:40:09] catboard.blif │ ├── [2016-01-23_07:40:08] catboard.pcf │ ├── [2016-01-23_07:40:11] catboard.txt │ ├── [2016-01-23_07:40:06] catboard.v │ ├── [2016-01-23_07:40:08] catboard.ys │ └── [2016-01-23_06:39:58] pck_myhdl_10.vhd ├── [2016-01-23_07:44:51] test_sending31.py 2 directories, 51 files The related .vcd (signal trace) file you refer to seems to be missing, what is needed to fix this? Jan Coombs |
