[myhdl-list] simulation appears okay when programmed not getting all signals.
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[myhdl-list] simulation appears okay when programmed not getting all signals.
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From: Edward V. <dev...@sb...> - 2016-01-23 01:18:35
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Hello All, ran python test_sending31.py --test which generates tb.vcd see the png file below adding the signals clkInOut clock ld ld_o pp0 ss0 ex_sending.py uses from test_sending31.py import top_sending On the RPi2B with the CAT-Board python ex_sending.py generates iceriver/catboard.v, iceriver/catboard.pcf, and iceriver/catboard.bin set_io clock C8 set_io ss0 P9 set_io clkInOut T14 set_io ld_o R10 The signals are BCM23, BCM15, and BCM27. testing with gpio.py which reads the 3 GPIO only 2 signals toggle. clkInOut okay ld_o okay ss0 does not toggle. https://github.com/develone/jpeg-2000-test/blob/master/pc_fast_blinker_jpeg/test_sending.png I also tested with Xula2-LX9 with StickIt-MB on RPi2B same results as on CAT-Board. I swapped clkInOut & ss0 with same results. Can anyone suggest what could be the problem? Thanks Edward Vidal Jr. e-mail dev...@sb... 915-595-1613 |
