Re: [myhdl-list] Weird error

[Josy B. <jos...@gm...>]

 
> def dff(q,d,clk,rst):
> 
>         <at> always(clk.posedge,rst.posedge)
>        def logic():
>              if rst==1:
>                    q.next=0
>              else:
>                    q.next=d
> 
>        return logic
> 
> def param_reg(q,d,clk,rst,width=4,n=2):
> 
>       signal_list=[Signal(intbv(0)[width+1:]) for i in range(n+1)]
>       instance_list=[dff(signal_list[i+1],signal_list[i],clk,rst) for 
i 
> in range(n)]
> 
>        <at> always_comb
>       def logic():
>            signal_list[0].next=d
>            q.next=signal_list[n+1]
> 
>       return logic,instance_list
> 
> but I get the following error:AlwaysCombError: signal (signal_list) 
used 
> as inout in always_comb function argument
> 
> when i change the code of param_reg to :
> 
> def param_reg(q,d,clk,rst,width=4,n=2):
> 
>       signal_list=[Signal(intbv(0)[width+1:]) for i in range(n+1)]
>       instance_list=[dff(signal_list[i+1],signal_list[i],clk,rst) for 
i 
> in range(n)]
> 
>        <at> always_comb
>       def logic():
>            signal_list[0].next=d
>        <at> always_comb
>       def logic2():
>            q.next=signal_list[n+1]
> 
>       return logic,instance_list,logic2
> 
> It works fine. Do you know whats the problem?

This is a choice made by our BFDL. I suspect that at the time of MyHDL's 
initial creation it was an error (or not supported by synthesis tools) 
in Verilog. VHDL has no issue. I just tried a similar Verilog module 
with Quartus Prime, without any problem.
I commented out this section in _always_comb.py:
        inouts = v.results['inout'] | 
self.inputs.intersection(self.outputs)
        if inouts:
            raise AlwaysCombError(_error.SignalAsInout % inouts)

I currently don't have the time to make a PR for this ...

Regards,

Josy