[myhdl-list] best practices for use of signals

[Edward V. <dev...@sb...>]

Hello All,I am trying to take advantage of the parallel feature of a FPGA.  I want to send enough data to keep the FPGA working.
My JPEG-2000 application repeats 2 step many times first on 3 values lft sam rht for even samples of image then for odd.My current code is trying to 16 of these.  Which is require many signals.  Jan has stated that signals are expensivein FPGA application. 
I moved most of the signals out of my https://github.com/develone/jpeg-2000-test/blob/master/pc_fast_blinker_jpeg/test_top.py to  https://github.com/develone/jpeg-2000-test/blob/master/pc_fast_blinker_jpeg/jpeg_sig.py for the reason to make the code more readable.I would also like to index the signals easier.  Does any have any suggestion?My Code converts to a Verilog with this command.
python test_top.py --convertA test bench is created with 
python test_top.py --test
Also trying to determine what resources are needed in the FPGA.
Any and all help is welcomed.Thanks in advance. 
 Edward Vidal Jr. e-mail dev...@sb... 915-595-1613