Re: [myhdl-list] parallel to serial
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Re: [myhdl-list] parallel to serial
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From: Edward V. <dev...@sb...> - 2016-01-16 01:23:00
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Hello All,What Chris provided worked okay.Jan is correct in one of tries the code converted but would not simulate.The https://github.com/develone/jpeg-2000-test/blob/master/pc_fast_blinker_jpeg/para2ser.py was added to my https://github.com/develone/jpeg-2000-test/blob/master/pc_fast_blinker_jpeg/test_top.py python test_top.py --test is a simulation python test_top.py --convert generates a Verilog file. Placing the files para2ser.py, ex_catboard_jpeg.py, jpeg.py, l2r.py, sh_reg.py, signed2twoscomplement.py, and test_top.py in my rhea/examples/build folder. This done on a Ubuntu 12.04 with Xilinx 14.6 also testing on RPi2B w/Yosys, Arachne-pnr, and ICEPack Should I be seeing more usage with around 30 plus instances?see below vidal@ws009:~/wkg/rhea/examples/build$ python ex_jpeg_xula2.py ** ToVerilogWarning: Signal is driven but not read: ss0 ** ToVerilogWarning: Signal is not driven: ld ** ToVerilogWarning: Signal is not driven: si1 ** ToVerilogWarning: Signal is not driven: si0 ** ToVerilogWarning: Signal is not driven: sig1 ** ToVerilogWarning: Signal is not driven: sig0 ** ToVerilogWarning: Signal is not driven: sig3 ** ToVerilogWarning: Signal is not driven: sig2 ** ToVerilogWarning: Signal is not driven: sig5 ** ToVerilogWarning: Signal is not driven: sig4 ** ToVerilogWarning: Signal is not driven: sig7 ** ToVerilogWarning: Signal is not driven: sig6 ** ToVerilogWarning: Signal is driven but not read: z4 ** ToVerilogWarning: Signal is driven but not read: z5 ** ToVerilogWarning: Signal is driven but not read: done5 ** ToVerilogWarning: Signal is driven but not read: done4 ** ToVerilogWarning: Signal is driven but not read: done7 ** ToVerilogWarning: Signal is driven but not read: done6 ** ToVerilogWarning: Signal is driven but not read: done1 ** ToVerilogWarning: Signal is driven but not read: done0 ** ToVerilogWarning: Signal is driven but not read: done3 ** ToVerilogWarning: Signal is driven but not read: done2 ** ToVerilogWarning: Signal is driven but not read: z6 ** ToVerilogWarning: Signal is driven but not read: z7 ** ToVerilogWarning: Signal is driven but not read: z0 ** ToVerilogWarning: Signal is driven but not read: z1 ** ToVerilogWarning: Signal is driven but not read: z2 ** ToVerilogWarning: Signal is driven but not read: z3 ** ToVerilogWarning: Signal is not driven: fB3 ** ToVerilogWarning: Signal is not driven: fB2 ** ToVerilogWarning: Signal is driven but not read: po6 ** ToVerilogWarning: Signal is driven but not read: po4 ** ToVerilogWarning: Signal is driven but not read: po2 ** ToVerilogWarning: Signal is driven but not read: po1 ** ToVerilogWarning: Signal is not driven: pp0 ** ToVerilogWarning: Signal is not driven: fB7 ** ToVerilogWarning: Signal is not driven: si6 ** ToVerilogWarning: Signal is not driven: reset ** ToVerilogWarning: Signal is not driven: si5 ** ToVerilogWarning: Signal is not driven: si4 ** ToVerilogWarning: Signal is driven but not read: po7 ** ToVerilogWarning: Signal is driven but not read: po5 ** ToVerilogWarning: Signal is driven but not read: po3 ** ToVerilogWarning: Signal is driven but not read: po0 ** ToVerilogWarning: Signal is not driven: si3 ** ToVerilogWarning: Signal is not driven: si2 ** ToVerilogWarning: Signal is not driven: fB1 ** ToVerilogWarning: Signal is not driven: fB0 ** ToVerilogWarning: Signal is not driven: si7 ** ToVerilogWarning: Signal is not driven: fB6 ** ToVerilogWarning: Signal is not driven: fB5 ** ToVerilogWarning: Signal is not driven: fB4 removing xilinx/xula2.v moving xula2.v --> xilinx/ Project name : xula2.xise Number of Slice Registers: 0 out of 11,440 0% Number of LUT Flip Flop pairs used: 0 Number of Slice Registers: 0 out of 11,440 0% Number of LUT Flip Flop pairs used: 0 {'fmax': -1, 'syn': {'dsp': (0, 2, 0), 'reg': (0, 11440, 0)}} removing xilinx/xula2.v moving xula2.v --> xilinx/ Project name : xula2.xise Number of Slice Registers: 0 out of 11,440 0% Number of LUT Flip Flop pairs used: 0 Number of Slice Registers: 0 out of 11,440 0% Number of LUT Flip Flop pairs used: 0 {'fmax': -1, 'syn': {'dsp': (0, 2, 0), 'reg': (0, 11440, 0)}} Thanks for the help. Edward Vidal Jr. e-mail dev...@sb... 915-595-1613 On Friday, January 15, 2016 3:39 PM, Jan Decaluwe <ja...@ja...> wrote: On 15/01/16 18:45, Edward Vidal wrote: > Hello All, > I can not believe that 3 lines are such a problem. > This t.next = (temp[36:35]) generates t <= temp(36-1 downto 35)(0); > which does not appear correct. Why not? But still, if working with single bits, why don't you simply assign an index instead of a slice? > This temp[36:1].next = temp[35:0] generates temp(36-1 downto 1) <= temp(35-1 downto 0); > which be taking the lower 34 bits to upper 34 of temp. That makes no sense in MyHDL, and will not simulate. Hence, you cannot draw any conclusions from conversion, even if it doesn't complain. Simulate first. > I am using @always(clk.posedge) could this be the problem? No. -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com World-class digital design: http://www.easics.com ------------------------------------------------------------------------------ Site24x7 APM Insight: Get Deep Visibility into Application Performance APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month Monitor end-to-end web transactions and take corrective actions now Troubleshoot faster and improve end-user experience. Signup Now! http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140 _______________________________________________ myhdl-list mailing list myh...@li... https://lists.sourceforge.net/lists/listinfo/myhdl-list |
