Re: [myhdl-list] Unsupported list comprehension form
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From: Jock T. <tan...@gm...> - 2016-01-15 03:37:24
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Chris, thank you for your swift reply! Speaking of boolean logic in Python, all() and any() seemed so well-placed and pythonic to me, I just could not imagine they are not supported. Thanks for the insight, I’ll continue struggling. 2016-01-15 13:04 GMT+10:00 Christopher Felton <chr...@gm...>: > The code that is convertible is limited, not all Python > constructs are supported. > > Your line of code (line 89): > > im_cl[i].next = im_gl[i] | any([(im_gl[j-1] if j > 0 else i_c) & > all(im_pl[j:i+1]) for j in range(i+1)]) > > Will need to be implemented with loops and basic conditional. > I am fairly sure "any" and "all" are not convertible. > > Refer to the manual to see what constructs are convertible: > > http://docs.myhdl.org/en/stable/manual/conversion.html#the-convertible-subset > > Regards, > Chris > > On 1/14/16 8:56 PM, Jock Tanner wrote: > >> Hello! >> >> I’m a Python web developer and a bit of radio hobbyist, and as such >> I’ve been playing with MyHDL for a couple of weeks. I’d like to >> apologize in advance if I have got some basics completely wrong from the >> start, because that’s pretty possible. But I’d like to get a bit of >> a clarification, or even better, an advice, concerning an error I >> recently stuck with. >> >> I’m trying to implement a carry-lookahead adder from >> http://www.ece.lsu.edu/ee3755/2013f/cla.pdf, and that’s how I wrote a >> carry generator part (from page 5): >> >> >> https://bitbucket.org/jock-tanner/asceticore/src/e0dce2f822639b66a024fe2f53ef2bcc98e8d2f2/components/adder.py?at=master&fileviewer=file-view-default#adder.py-64:92 >> >> The code simulates fine, but when I try to convert it to Verilog, the >> error comes up: >> >> “myhdl.ConversionError: in file >> >> /home/tanner/workspace/pr043-asceticore/project/asceticore/components/adder.py, >> line 89: >> >> Unsupported list comprehension form: should be [intbv()[n:] for i in >> range(m)]†>> Since I wish to put this design into an FPGA (I haven’t got the board >> yet, but definitely will), I consider the conversion part important. But >> right now I’m clueless of what I have done wrong conversion-wise. >> I’ve read the manual >> (http://docs.myhdl.org/en/stable/manual/conversion.html), but it >> didn’t get me any further. >> >> Any ideas about how I should rework my code? Sorry again for bothering >> you with such small and (hopefully) trivial matters. >> >> JT >> >> >> >> >> ------------------------------------------------------------------------------ >> Site24x7 APM Insight: Get Deep Visibility into Application Performance >> APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month >> Monitor end-to-end web transactions and take corrective actions now >> Troubleshoot faster and improve end-user experience. Signup Now! >> http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140 >> >> >> >> _______________________________________________ >> myhdl-list mailing list >> myh...@li... >> https://lists.sourceforge.net/lists/listinfo/myhdl-list >> >> > > > > > ------------------------------------------------------------------------------ > Site24x7 APM Insight: Get Deep Visibility into Application Performance > APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month > Monitor end-to-end web transactions and take corrective actions now > Troubleshoot faster and improve end-user experience. Signup Now! > http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140 > _______________________________________________ > myhdl-list mailing list > myh...@li... > https://lists.sourceforge.net/lists/listinfo/myhdl-list > > |