Re: [myhdl-list] parallel to serial

[Christopher F. <chr...@gm...>]

Edward,

When assign intbv bit slices you need to:

     temp.next[1:0] = 0

Hope that helps,
Chris

On 1/14/16 8:26 PM, Edward Vidal wrote:
> Hello All,
> I found this VHDL code on the web.
> library ieee;
> use ieee.std_logic_1164.all;
>
> entity piso is
>      port(
>           clk,load  : in std_logic;
>           pi        : in std_logic_vector(35 downto 0);
>           so        : out std_logic);
> end piso;
>
> architecture arch of piso is
>
>      signal t   : std_logic;
>      signal temp: std_logic_vector(35 downto 0);
>
> begin
>
>     process (clk,pi,load)
>      begin
>         if (load='1') then
>               temp(35 downto 0) <= pi(35 downto 0);
>         elsif (CLK'event and CLK='1') then
>               t <= temp(35);
>               temp(35 downto 1) <= temp(34 downto 0);
>               temp(0) <= '0';
>         end if;
>      end process;
>
> so <= t;
>
> end arch;
> I create a test bench in ise and it appears to be okay.
> from myhdl import *
> import argparse
> W0 = 36
> pp0 = Signal(intbv(0)[W0:])
> ss0 = Signal(bool(0))
> clk = Signal(bool(0))
> ld = Signal(bool(0))
> def cliparse():
>      parser = argparse.ArgumentParser()
>      parser.add_argument("--build", default=False, action='store_true')
>      parser.add_argument("--test", default=False, action='store_true')
>      parser.add_argument("--convert", default=False, action='store_true')
>      args = parser.parse_args()
>      return args
>
> def para2ser(clk, pp0, ss0, ld):
>
>      t = Signal(bool(0))
>      temp = Signal(intbv(0)[W0:])
>      @always(clk.posedge)
>      def logic():
>
>          if (ld == 1):
>            temp[36:0].next = pp0[36:0]
>          else:
>            t.next = int(temp[36:35])
>
>            temp[36:1].next = temp[35:0]
>            temp[1:].next = int(0)
>          ss0.next = t
>
>      return logic
>
> def tb(clk, pp0, ss0, ld):
>      instance_1 = para2ser(clk, pp0, ss0, ld)
>
>      @always(delay(10))
>      def clkgen():
>          clk.next = not clk
>      @instance
>      def stimulus():
>
>          pp0.next = 34359738368
>          yield clk.posedge
>          ld.next = 1
>          yield clk.posedge
>          ld.next = 0
>          yield clk.posedge
>          print ("%s %d") % (bin(pp0,36), ss0 )
>          for i in range(36):
>              yield clk.posedge
>              print ("%d %s  %d") % (i, bin(pp0,36), ss0 )
>          raise StopSimulation
>
>      return instances()
> def convert(args):
>      toVHDL(para2ser,clk, pp0, ss0, ld)
>      toVerilog(para2ser,clk, pp0, ss0, ld)
>
>
> def main():
>      args = cliparse()
>      if args.test:
>         tb_fsm = traceSignals(tb,clk, pp0, ss0, ld)
>         sim = Simulation(tb_fsm)
>         sim.run()
>      if args.convert:
>          convert(args)
>
> if __name__ == '__main__':
>      main()
> Can someone tell me what I am doing wrong?
> I think it this line
> temp[1:].next = int(0)
> I have tried without the int and I get the same results when I run
> python para2ser.py --test
> Thanks
> Regards,
> Edward Vidal Jr. e-mail dev...@sb... 915-595-1613
>
>
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