Re: [myhdl-list] Asynchronous double port RAM

[Nicolas P. <ni...@aa...>]

Le 11/01/2016 14:26, Josy Boelen a écrit :
> Hi Nicolas,
>
> I slightly modified your code to have Quartus Prime infer a RAM :)
>
>      @myhdl.always(clka.posedge)
>      def portA():
>          doa.next = ram[addra]
>          if ena :
>              if wea :
>                  ram[addra].next = dia
>
>      @myhdl.always(clkb.posedge)
>      def portB():
>          dob.next = ram[addrb]
>          if enb :
>              if web :
>                  ram[addrb].next = dib
> as Quartus needs a register on the output path I moved the read-
> statement before the enable.
>
> Apparently Quartus Prime has no problem with *ram* being a *signal*
> rather than a *shared variable*. Although in  the "Recommended HDL
> Coding Styles" they also show the example with a *shared variable*.
>
> I have no idea whether Vivado and ISE are also forgiving.
The code I sent in my first message has been formatted following Xilinx 
rules.
However, I did not tried to compile it with Xilinx tools. I'll have a 
try and tell you.
>
> Your other request: initialising the ram-array is not that much work.
> I'll try to submit a PR shortly.
That's good news :)

Thanks
Nicolas
>
> Regards,
>
> JOsy
>
>
>
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*** ni...@aa... <mailto:ni...@aa...>

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