Re: [myhdl-list] Asynchronous double port RAM

[Josy B. <jos...@gm...>]

Nicolas Pinault <nicolas <at> aaton.com> writes:

> 
> 
>     Hi,
>     I am experimenting with asynchronous DPR (ie : with 2 clock 
domains)
>     Here is my code :
<snip>
>     The generated VHDL code is not correct. 
>     ram array is declared as a signal while this is not correct since 
2
>     processes access this object. 
>     ram array should be declared as a shared variable. Right ?
>     Simulation seems to be ok.
>     Nicolas-- 
<snip>

Hi Nicolas,

I slightly modified your code to have Quartus Prime infer a RAM :)

    @myhdl.always(clka.posedge)
    def portA():
        doa.next = ram[addra]
        if ena :
            if wea :
                ram[addra].next = dia

    @myhdl.always(clkb.posedge)
    def portB():
        dob.next = ram[addrb]
        if enb :
            if web :
                ram[addrb].next = dib
as Quartus needs a register on the output path I moved the read-
statement before the enable.

Apparently Quartus Prime has no problem with *ram* being a *signal* 
rather than a *shared variable*. Although in  the "Recommended HDL 
Coding Styles" they also show the example with a *shared variable*.

I have no idea whether Vivado and ISE are also forgiving.

Your other request: initialising the ram-array is not that much work. 
I'll try to submit a PR shortly.

Regards,

JOsy