[myhdl-list] Ram initialisation

[Nicolas P. <ni...@aa...>]

Hi,

I am trying to generate a RAM with initial values.

Here is the code :
def MemoryGene1000Hz(
...
                     ):

     data_length = len(dia)

     # Instanciate RAM array
     ram = [Signal(intbv(0)[data_length:]) for i in range(2**len(addra))]

     # Init RAM with full scale sinus (48 samples)
     scale_factor = (2**(data_length-1)) - 1
     for i in range(48) :
         v = int(sin(i*2*pi/48) * scale_factor)
         ram[i] = Signal(intbv(v)[data_length:])
         #print(i, "%6.6X" % ram[i])

     ...

VHDL code generated is as follows :
type t_array_ram is array(0 to 256-1) of unsigned(23 downto 0);
signal ram: t_array_ram;

The ram array is not initialised.

Bug or bad code ?

Nicolas

-- 
*Nicolas PINAULT
R&D electronics engineer
*** ni...@aa... <mailto:ni...@aa...>

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