Re: [myhdl-list] rhea & cores

[Edward V. <dev...@sb...>]

Chris ,The example you  provided should also work with a XulA2-LX9 is that correct?I have downloaded IceCube2 but have not installed it?  Which version of IceCube2 have you tested Linux or window?I normally work on a Ubuntu 12.04 this is where I have the Xilinx 14.6.Which board has the highest priority? 
I also have been looking at the Parallella & zybo.Are these 2 boards easier to work with than the Zedboard.  I have an Yocto O/S working but nothing in the FPGA side.Are you working on theses board using the Zynq 7000?

Regards,
Thanks 
 Edward Vidal Jr. e-mail dev...@sb... 915-595-1613 

    On Tuesday, December 29, 2015 3:31 PM, Christopher Felton <chr...@gm...> wrote:
 

 On 12/29/15 3:28 PM, Edward Vidal wrote:
> Hi Chris,
> Thanks for all the help it is appreciated.
>
> Which of the cores in the rhea package are ready to add to a design?

Sorry to disappoint, this is all beta and
probably will be for awhile but with that
said many of the cores are usable.  To
determine if they are can be some work
until documentation etc. is complete ...

>
> I am looking at using  the CAT-Board or XulA2-LX9 & StickIt-MB with a RPiB.
>
> In rhea/rhea/cores/uart/ there 2 cores uart.py & uartlite.py.
> Do you add both?
> python test_uart.py --convert --test uart is this not functional yet?  I
> did not see

No, one of the places to look is the __init__.py
in each of the core directories.  It will give you
indicate which are the top-levels and then you
import

    from rhea.cores.uart import uartlite

See the following example:
https://github.com/cfelton/rhea/blob/master/examples/boards/icestick/icestick_blinky_host.py

In general, it is best to look at the examples
versus the tests.  The above example I have
tested on the IceStick.  But note, the above
example did not work with Yosys+APaR when I
tried it but it does work with IceCube2.

Hope that helps,
Chris



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