Re: [myhdl-list] rhea & cores

[Christopher F. <chr...@gm...>]

On 12/29/15 3:28 PM, Edward Vidal wrote:
> Hi Chris,
> Thanks for all the help it is appreciated.
>
> Which of the cores in the rhea package are ready to add to a design?

Sorry to disappoint, this is all beta and
probably will be for awhile but with that
said many of the cores are usable.  To
determine if they are can be some work
until documentation etc. is complete ...

>
> I am looking at using  the CAT-Board or XulA2-LX9 & StickIt-MB with a RPiB.
>
> In rhea/rhea/cores/uart/ there 2 cores uart.py & uartlite.py.
> Do you add both?
> python test_uart.py --convert --test uart is this not functional yet?  I
> did not see

No, one of the places to look is the __init__.py
in each of the core directories.  It will give you
indicate which are the top-levels and then you
import

     from rhea.cores.uart import uartlite

See the following example:
https://github.com/cfelton/rhea/blob/master/examples/boards/icestick/icestick_blinky_host.py

In general, it is best to look at the examples
versus the tests.  The above example I have
tested on the IceStick.  But note, the above
example did not work with Yosys+APaR when I
tried it but it does work with IceCube2.

Hope that helps,
Chris