[myhdl-list] rhea & cores

[Edward V. <dev...@sb...>]

Hi Chris,Thanks for all the help it is appreciated.
Which of the cores in the rhea package are ready to add to a design?
I am looking at using  the CAT-Board or XulA2-LX9 & StickIt-MB with a RPiB.
In rhea/rhea/cores/uart/ there 2 cores uart.py & uartlite.py.Do you add both?python test_uart.py --convert --test uart is this not functional yet?  I did not see
In rhea/rhea/models/uart/_uart_model.py  this is not added to the design is that 
correct?This works python test_uart.py --trace --test uartls output/vcd
_bench_uart.vcd 
This works okay gtkwave  output/vcd/_bench_uart.vcd.
Adding a method to pass data from the host to the fpga has been my greatest issue.I was hoping to use several GPIO to speed up the transfer of an image to the FPGA.Transferring an image over the USB takes a considerable amount of time.
This is from the e-mail that I sent you on 12/3/15.
Also in test_jpeg 

The option is python  test_jpegenc.py --vtracegtkwave vcd/_tb_jpegenc.vcd 

GTKWave Analyzer v3.3.34 (w)1999-2012 BSI

No symbols in VCD file..is it malformed?  Exiting!
Regards,

Edward Vidal Jr. e-mail dev...@sb... 915-595-1613