Re: [myhdl-list] adding files to top-level with rhea

[Christopher F. <chr...@gm...>]

Edward,

The the Xula2 already exists, you can use the
Xula2.

    from rhea.build.boards.xilinx import Xula2

https://github.com/cfelton/rhea/blob/master/rhea/build/boards/xilinx/__init__.py#L4

Regards,
Chris

On Wed, Dec 23, 2015 at 3:00 PM, Edward Vidal <dev...@sb...>
wrote:

> Chris,
> I see what you did with  my_board_def.py.  The problem I am having is in
> the file
> rhea/rhea/build/boards/xilinx/_xula.py device = 'XC6SLX25'.  I need to
> override to device = 'XC6SLX9'.
> There are 2 versions xula2.
>
> I tried make test instead of make.
> Thanks,
>
>
>
> Edward Vidal Jr. e-mail dev...@sb... 915-595-1613
>
>
> On Wednesday, December 23, 2015 9:16 AM, Christopher Felton <
> chr...@gm...> wrote:
>
>
> On 12/21/15 10:05 AM, Edward Vidal wrote:
> > Hello All,
> >
> > Yosys & arachne-pnr appear to work very well compared to Xilinx ISE.
> > It takes 2:41 to generate xula2.bit, while it only takes 0:35 to
> > generate the catboard.bin.
> >
>
> Not to diminish the efforts of the open-source
> synthesis and PaR but run-time is a small
> benefit when compared to the resource and
> timing results.  In other-words, if the flow
> executes quickly but uses twice as many
> resources it isn't a good comparison.
>
> > On the RPi2B with CAT-Board the first 2 leds appeared to always be on.
> > See the changes to blink.py in the file attached chgs_blink.txt.
> > I choose 12000000 since the freq. on my XulA2-LX9 is 12000000 Hz.
> > Using 1440000 on the XulA2-LX9 would be 8.333333 times.
> > Now, 2 leds on XulA2-LX9 with StickIt-MB and RPi2B appear to blink at
> > the same rate as leds on CAT-Board with RPi2B.
> >
>
> I haven't looked at your code, one thing you
> might want to do is verify your design works
> with the IceCub2 as well as Yosys+Ar, in
> my testing I have had icestick designs work
> with IceCube and not with Yosys.  I plan on
> adding the IceCub2 flow to the rhea.build but
> it is farther down on my list of things to do.
>
> > I generated the docs in both html & latexpdf formats.
> >
> > Running make in rhea/test appears to work okay.
> > The test_models/test_fx2_model.py just hangs up. Should the be expected
> > at this point?
>
> Yes, there seems to be an issue with py.test
> that I haven't figured out yet.  If you run
> `make test` it will run all the same tests
> but not using py.test.
>
> >
> > In the file ex_xula2.py I added the flow.add_files line.
> >      flow.add_files('jpeg_cat.v')
> >      flow.run()
> > Running ISE I see the file jpeg_cat.v is now part of the project.
> > What do I need to do, to have jpeg_cat.v instantiated in the xula2.v?
> > Or do I have to do this manually?
>
> You have to do this manually, there is an
> undocumented (beta) feature that might help
> (`verilog_instance`) otherwise the documented
> approach is to us `verilog_code` and create a
> wrapper for the module you want instantiate.
>
>
> >
> > Does anyone have a MyHDL or Verilog for a DCM?
> > I have been using the one in Xess VHDL_Lib
> >
>
> I have been slowly adding some vendor agnostic
> primitives to rhea, one of these is a clock
> manager (PLL/DCM/MMCM):
>
> https://github.com/cfelton/rhea/blob/master/examples/boards/de0nano_soc/device_primitives/de0nano_soc_device_prims.py#L20
>
> But I have only limited testing, you might
> not want to use it unless you are willing to
> debug and make changes.
>
> Regards,
> Chris
>
>
>
>
>
> ------------------------------------------------------------------------------
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>
>
>
>
> ------------------------------------------------------------------------------
>
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>
>