Re: [myhdl-list] rhea AssertionError

[Christopher F. <chr...@gm...>]

On 12/17/2015 10:15 AM, Edward Vidal wrote:
> Hello All,I am using the examples from https://github.com/xesscorp/CAT-Board
>
> My code is at https://github.com/develone/jpeg-2000-test/tree/master/jpeg_cat
> python buttons_display.py creates buttons_display.v with my signals and
> module BUTTONS_DISPLAY_JPEG_RTL.  These signals are not connected to any FPGA
> pins. Several signals use brd.add_port('d0_o', 'A11') in the file ex_catboard_buttons.py.
>
> How do you add a port to a signal not connected to a pin?
>

You can't at least not with the current implementation.
The FPGA toolflow automation assumes you are building
for a particular development board, all top-level ports
need to be assigned to a pin.

It doesn't preclude you from creating a design with any
combination for ports just from automatically mapping a
top-level module to an FPGA board.

The main goal of the tool automation is to take a top-level
MyHDL design and automatically map it to a development
board.  If the port names don't match the pin names in
the dev board definition (typically the names from the
documentation) then there is some work to manually map
the ports to pins.

Now, if you don't really want to target a dev board but
want to see if a module will synthesize - this is currently
not support but it is something I can possibly add with
little effort.

Hope that helps,
Chris