[myhdl-list] rhea AssertionError

[Edward V. <dev...@sb...>]

Hello All,I am using the examples from https://github.com/xesscorp/CAT-Board

My code is at https://github.com/develone/jpeg-2000-test/tree/master/jpeg_cat
python buttons_display.py creates buttons_display.v with my signals and
module BUTTONS_DISPLAY_JPEG_RTL.  These signals are not connected to any FPGA 
pins. Several signals use brd.add_port('d0_o', 'A11') in the file ex_catboard_buttons.py.

How do you add a port to a signal not connected to a pin?

I have tried brd.add_port('left_i', 'NONE') for my signals.

python ex_catboard_buttons.py 
Traceback (most recent call last):
  File "ex_catboard_buttons.py", line 53, in <module>
    run_catboard()
  File "ex_catboard_buttons.py", line 49, in run_catboard
    flow.run()
  File "build/bdist.linux-armv7l/egg/rhea/build/toolflow/_iceriver.py", line 84, in run
  File "build/bdist.linux-armv7l/egg/rhea/build/toolflow/_convert.py", line 30, in convert
  File "build/bdist.linux-armv7l/egg/rhea/build/_fpga.py", line 239, in get_portmap
AssertionError: Error unspecified port left_i


Thanks, Edward Vidal Jr. e-mail dev...@sb... 915-595-1613