Re: [myhdl-list] Signal names for verilog conversion of interfaces

[Josy B. <jos...@gm...>]

Hi Richard,


it is a (subtle) bug. Subtle because probably the case of a module only 
having _interface_ type ports never has been imagined?

BTW. I rewrote your top-module slightly, adding Signals in the toVerilog() 
call:
    def iftest_top(i1, o1, i2, o2, clk):
        test_instance1 = test_logic(i1, o1, clk)
        test_instance2 = test_logic(i2, o2, clk)

        return test_instance1, test_instance2

    toVerilog(iftest_top, i1, o1, i2, o2, clk)

otherwise the conversion ends up with no module ports and multiple 
warnings.

Regards,

Josy